US2023305245A1PendingUtilityA1

Techniques for optical sub-assembly and packaging

Assignee: AEVA INCPriority: Oct 5, 2021Filed: May 22, 2023Published: Sep 28, 2023
Est. expiryOct 5, 2041(~15.2 yrs left)· nominal 20-yr term from priority
H10W 40/28H10W 90/00H10H 20/8584H01S 5/0239G02B 6/4271H01S 5/02415H01L 33/645G02B 6/43H10N 19/00H01S 5/50H01S 5/02365H01S 5/02325H01S 5/021H01S 5/02476
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Claims

Abstract

A method of cooling an optical sub-assembly includes operating a diode mounted to a diode submount structure and cooling the diode with a thermoelectric cooler (TEC) in thermal contact with the diode, wherein the diode is positioned between the diode submount structure and the TEC.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A method of cooling an optical sub-assembly comprising:
 operating a diode mounted to a diode submount structure; and   cooling the diode with a thermoelectric cooler (TEC) in thermal contact with the diode, wherein the diode is positioned between the diode submount structure and the TEC.   
     
     
         2 . The method of  claim 1 , wherein the diode submount structure is a silicon photonics (SiPho) die. 
     
     
         3 . The method of  claim 2 , wherein the SiPho die comprises a waveguide, and light from the diode exits the SiPho die via the waveguide. 
     
     
         4 . The method of  claim 3 , wherein the SiPho die is positioned over the TEC and overhangs the TEC to prevent an underfill material from covering the waveguide. 
     
     
         5 . The method of  claim 4 , wherein the SiPho die overhangs the TEC by between 1-2 mm. 
     
     
         6 . The method of  claim 1 , wherein the diode submount structure is an aluminum nitride sub-mount structure. 
     
     
         7 . The method of  claim 1 , wherein cooling the diode comprises directly cooling the diode mounted between the diode submount structure and the TEC. 
     
     
         8 . The method of  claim 1 , further comprising:
 cooling one or more integrated circuits electrically connected to the diode submount structure.   
     
     
         9 . The method of  claim 8 , wherein the one or more integrated circuits are positioned between the diode submount structure and the TEC. 
     
     
         10 . The method of  claim 1 , wherein the TEC includes a top surface facing away from a housing with electrical interconnects, and a bottom surface mounted to the housing, and the diode is directly connected to the top surface of the TEC. 
     
     
         11 . A system for cooling diodes, comprising:
 a housing with electrical interconnects;   a thermoelectric cooler (TEC) positioned on the housing;   a silicon photonics (SiPho) die; and   a plurality of diodes mounted to the SiPho die, wherein each of the plurality of diodes are positioned between the SiPho die and the TEC and in direct thermal communication with both the SiPho die and the TEC.   
     
     
         12 . The system of  claim 11 , further comprising one or more integrated circuits positioned between the SiPho die and the TEC and in direct thermal communication with both the SiPho die and the TEC. 
     
     
         13 . The system of  claim 12 , wherein the one or more integrated circuits are electrically coupled to the SiPho die. 
     
     
         14 . The system of  claim 11 , wherein the SiPho die is offset from the TEC in a horizontal direction. 
     
     
         15 . The system of  claim 14 , wherein the SiPho die is positioned over the TEC and overhangs the TEC to prevent an underfill material from covering an output waveguide. 
     
     
         16 . The system of  claim 15 , wherein the SiPho die overhangs the TEC by between 1-2 mm. 
     
     
         17 . The system of  claim 15 , wherein the underfill material is a thermally conductive and electrically insulating material. 
     
     
         18 . The system of  claim 11 , wherein each of the plurality of diodes comprises a light emitting diode for emitting an optical beam. 
     
     
         19 . The system of  claim 18 , wherein the SiPho die comprises a plurality of waveguides, wherein the optical beam emitted by each of the plurality of diodes exits the SiPho die via a corresponding waveguide of the plurality of waveguides. 
     
     
         20 . The system of  claim 11 , wherein the TEC includes a top surface facing away from a housing with electrical interconnects, and a bottom surface mounted to the housing, and each of the plurality of diodes is directly connected to the top surface of the TEC.

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