Core group memory processsing with mac reuse

Abstract

A multi-accumulator multiply-and-accumulate (MAC) unit can include a multiplier and a plurality of accumulators. The multiplier can be configured to multiply a given element of a corresponding column of a first matrix and a plurality of elements of a corresponding row of a second matrix to generate a plurality of corresponding partial product elements that can be accumulated by corresponding ones of the plurality of accumulators.

What is claimed is: 
     
         1 . A memory processing unit (MPU) comprising:
 a first memory including a plurality of memory regions; and   a plurality of processing regions interleaved between the plurality of regions of the first memory, wherein the processing regions include a plurality of computer cores, wherein the plurality of compute cores are coupled between adjacent ones of the plurality of memory regions, wherein the compute cores include multi-accumulator multiply-and-accumulate (MAC) unit configured to computer matrix dot products wherein element values of a given matrix are reused by time division multiplexing computations of the matrix dot product.   
     
     
         2 . The memory processing unit of  claim 1 , wherein each multi-accumulator multiply-and-accumulate unit includes a multiplier and a plurality of accumulators configured to accumulate corresponding partial products of the matrix dot product computed by the multiplier in corresponding ones of a plurality of accumulators. 
     
     
         3 . The memory processing unit of  claim 2 , wherein the number of accumulators of each multi-accumulator multiply-and-accumulate unit is configured based on a number of physical channels. 
     
     
         4 . The memory processing unit of  claim 3 , wherein the number of physical channels and the number of the plurality of computer cores configured to compute the matrix dot product are selected based on a specified computation utilization of the plurality of compute cores. 
     
     
         5 . A memory processing unit (MPU) comprising:
 a first memory including a plurality of memory regions, wherein the plurality of memory regions are configured in corresponding pluralities of memory blocks; and   a plurality of processing regions interleaved between the plurality of regions of the first memory, wherein the processing regions include a plurality of core groups of compute cores configurable in one or more clusters, wherein the plurality of core groups of respective ones of the plurality of processing regions are coupled between adjacent ones of the plurality of memory regions of the first memory and between adjacent core groups coupled to respective adjacent memory regions, and wherein compute cores are configured to compute a plurality of output feature map values simultaneously without reloading weight values.   
     
     
         6 . The memory processing unit of  claim 5 , wherein at least one of the plurality of core groups include a plurality of near memory (M) compute cores, wherein the plurality of near memory (M) compute cores each comprise a multiplier and a plurality of accumulators configured to time multiplex computation of a dot product of a first matrix and a second matrix wherein element values of the first matrix are reused. 
     
     
         7 . The memory processing unit of  claim 5 , wherein a number of the plurality of compute cores in one or more of the core groups each include a multiply-and-accumulate (MAC) unit including a multiplier and a plurality of accumulators. 
     
     
         8 . The memory processing unit of  claim 6 , wherein:
 the multiplier is configured to compute corresponding partial products of the matrix dot product reusing a given element of first matrix; and   the plurality of accumulators are configured to corresponding partial products of the matrix dot product computed by the multiplier.   
     
     
         9 . A method comprising:
 receiving, by a plurality of multi-accumulator multiply-and-accumulate (MAC) units, a first matrix and a second matrix;   multiplying, by the plurality of multi-accumulator multiply-and-accumulate (MAC) units, element values of the first matrix with a plurality of element values of the second matrix to generate a corresponding plurality of partial products; and   accumulating, by the plurality of multi-accumulator multiply-and-accumulate (MAC) units, the plurality of partial products in respective accumulators of the multi-accumulator multiply-and-accumulate (MAC) units.   
     
     
         10 . The method according to  claim 9 ,
 loading a current weight value from the one or more memory devices into a plurality of multiply and accumulate units, and a plurality of adjacent current input feature map values from the one or more memory devices into respective multiply and accumulate units:   performing corresponding multiply and accumulate operations using the current weight value and corresponding ones of the plurality current input feature map values to generate corresponding current accumulated values by the respective multiply and accumulate units;   iterating through corresponding input channels of input feature map and corresponding input channels of weights;   iterating through kernel height and kernel width of weights, and corresponding map width and map height in the input feature map;   outputting corresponding current accumulated values as corresponding output feature map values;   resetting the corresponding current accumulated values and iterating through map width and map height of input feature map, and corresponding kernel height and kernel width of weights; and   iterating through filters of weights.