Systolic random number generator

Abstract

Systems and methods for a random number generator including a systolic array to provide a random number output. In one approach, the systolic array can be arranged in two or greater dimensions, and each cell of the array comprises a ring oscillator. Data is read from a random access memory to provide the inputs to the systolic array. A linear feedback shift register receives the random number output as a feedback signal used to address the memory to read data to provide as the inputs to the systolic array.

1 - 20 . (canceled) 
     
     
         21 . A random number generator comprising:
 a plurality of cells configured in an at least two-dimensional array, each cell comprising an oscillator, wherein the at least two-dimensional array is arranged to provide a random number output;   a physical unclonable function configured to provide input to the at least two-dimensional array; and   a shift register configured to receive the random number output from the systolic array and to provide a feedback signal to the physical unclonable function for selecting the input.   
     
     
         22 . The random number generator of  claim 21 , wherein the oscillator in each cell is a ring oscillator. 
     
     
         23 . The random number generator of  claim 21 , wherein the physical unclonable function comprises a memory device. 
     
     
         24 . The random number generator of  claim 23 , wherein the feedback signal is used to address the memory device. 
     
     
         25 . The random number generator of  claim 21 , wherein the physical unclonable function, as directed by the shift register, is used to seed the oscillators in the systolic array. 
     
     
         26 . The random number generator of  claim 21 , wherein each cell further comprises a flip-flop configured to receive an output from the oscillator and to provide an input to an exclusive OR gate. 
     
     
         27 . The random number generator of  claim 26 , wherein the exclusive OR gate is further coupled to receive inputs from two adjacent cells in the at least two-dimensional array. 
     
     
         28 . The random number generator of  claim 26 , wherein the flip-flop is a first flop-flop, and wherein each cell further comprises a second flip-flop coupled to receive an input from the exclusive OR gate and to provide an output to an adjacent cell in the at least two-dimensional array. 
     
     
         29 . The random number generator of  claim 21 , further comprising a clock configured to provide a signal to control providing of the feedback signal to the physical unclonable function. 
     
     
         30 . The random number generator of  claim 21 , wherein the shift register comprises a linear feedback shift register. 
     
     
         31 . A system comprising:
 a plurality of cryptographic modules each configured to process packets, wherein the packet processing includes encrypting a packet based on a security key associated with the packet; and   a systolic array configured to receive a plurality of inputs, and to provide a random number output to one or more of the plurality of cryptographic modules.   
     
     
         32 . The system of  claim 31 , further comprising:
 memory configured to provide the inputs to the systolic array, and further coupled to receive a signal based on the random number output, wherein the signal is used for selecting the inputs provided to the systolic array.   
     
     
         33 . The system of  claim 31 , further comprising:
 a first interface coupled to the plurality of cryptographic modules and configured to receive an incoming packet, associate a first security key with the incoming packet, select one of the plurality of cryptographic modules, and route the incoming packet to the selected cryptographic module.   
     
     
         34 . The system of  claim 31 , wherein the systolic array comprises a plurality of cells, each cell including an oscillator. 
     
     
         35 . The system of  claim 31 , further comprising a shift register configured to:
 receive the random number output; and   provide an output used for addressing the memory to select the inputs provided to the systolic array.   
     
     
         36 . A system comprising:
 a random number generator comprising:
 a systolic array configured to provide a random number value, wherein the systolic array comprises a plurality of cells, and each cell comprises an oscillator; 
   a plurality of programmable cryptographic devices, each cryptographic device configured to receive the random number value; and   at least one programmable input/output interface configured to route each of a plurality of incoming packets to one of the cryptographic devices for encryption.   
     
     
         37 . The system of  claim 36 , wherein:
 the programmable input/output interface is programmable to support different interface protocols, and   each of the plurality of cryptographic devices is programmable to support different encryption protocols.   
     
     
         38 . The system of  claim 36 , wherein each of the plurality of programmable cryptographic devices comprises at least one of a programmable systolic packet input engine, a programmable systolic cryptographic engine, or a programmable systolic packet output engine. 
     
     
         39 . The system of  claim 36 , wherein the oscillator is a free-running asynchronous oscillator. 
     
     
         40 . The system of  claim 39 , wherein each cell further comprises a flip-flop that receives an input signal from the oscillator.