US2023315388A1PendingUtilityA1

Multiply-Accumulate Circuit

77
Assignee: AMBIENT SCIENT INCPriority: Feb 21, 2019Filed: Apr 27, 2023Published: Oct 5, 2023
Est. expiryFeb 21, 2039(~12.6 yrs left)· nominal 20-yr term from priority
G06F 7/5443H03M 1/38G06F 2207/4824G06F 7/50G06F 17/16H03K 19/20
77
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Claims

Abstract

A multiply-accumulate circuit and methods for using the same are disclosed. In one embodiment, a multiply-accumulate circuit includes a memory configured to store a first set of operands and a second set of operands, where the first set of operands and the second set of operands are cross-multiplied to form a plurality of product pairs, a plurality of computation circuits configured to generate a plurality of charges according to the plurality of product pairs, and an aggregator circuit configured to aggregate the plurality of charges from the plurality of computation circuits to record variations of charges, where the variation of charges represent an aggregated value of the plurality of product pairs.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 - 20 . (canceled) 
     
     
         21 . A multiply-accumulate circuit, comprising:
 a memory configured to store a plurality of operands, wherein said plurality of operands are divided into a plurality of sets of operands wherein any two of said plurality of sets of operands are multiplied to form a plurality of product pairs;   a plurality of computation circuits configured to generate a plurality of charges according to said plurality of product pairs; and   an aggregator circuit configured to aggregate said plurality of charges from said plurality of computation circuits to record said charges.   
     
     
         22 . The multiply-accumulate circuit of  claim 21 , wherein each computation circuit in said plurality of computation circuits further comprises:
 a current multiplier circuit configured to convert a first operand of said computation circuit as a current that equals to a product of the first operand and a reference unit current; and   a time multiplier circuit configured to convert a second operand of said computation circuit as a duration that equals to a product of the second operand and a reference unit time period, wherein a charge is generated based on said current and said duration.   
     
     
         23 . The multiply-accumulate circuit of  claim 22 , wherein said current multiplier circuit comprises a plurality of current mirrors connected in parallel, wherein each current mirror in said plurality of current mirrors is configured to produce an output current. 
     
     
         24 . The multiply-accumulate circuit of  claim 23 , wherein a drive strength of each of said current mirrors is controlled. 
     
     
         25 . The multiply-accumulate circuit of  claim 22 , wherein said time multiplier circuit comprises a magnitude to time converter circuit. 
     
     
         26 . The multiply-accumulate circuit of  claim 25 , wherein said magnitude to time converter circuit comprises a plurality of toggle flip-flops connected in series and a reset circuit configured to reset the counter circuit. 
     
     
         27 . The multiply-accumulate circuit of  claim 22 , wherein said timer multiplier circuit further comprises:
 for a bit in said second operand;   a supplementary current multiplier circuit configured to produce a multiplied reference current based on said reference unit current and a magnitude represented by said second operand; and   a magnitude to time converter circuit.   
     
     
         28 . The multiply-accumulate circuit of  claim 21 , wherein said aggregator circuit further comprises:
 for each product pair in said plurality of product pairs, a charging circuit and a discharging circuit.   
     
     
         29 . The multiply-accumulate circuit of  claim 28 , wherein said charging circuit comprises:
 a charging switch coupled to a capacitor wherein charging of said capacitor is performed in response to said sign bit of said first operand and said sign bit of said second operand being the same.   
     
     
         30 . The multiply-accumulate circuit of  claim 28 , wherein said discharging circuit comprises:
 a discharging switch coupled to a capacitor wherein discharging of said capacitor is performed in response to said sign bit of said first operand and said sign bit of said second operand being different.   
     
     
         31 . A method of performing multiply-accumulate, comprising:
 storing, in a memory, a plurality of operands, wherein said plurality of operands are divided into a plurality of sets of operands wherein any two of said plurality of sets of operands are multiplied to form a plurality of product pairs;   generating, by a plurality of computation circuits, a plurality of charges according to said plurality of product pairs; and   aggregating, by an aggregator circuit, said plurality of charges from said plurality of computation circuits to record charges.   
     
     
         32 . The method of  claim 31 , wherein generating said plurality of charges comprises:
 for each computation circuit in said plurality of computation circuits,   converting, by a current multiplier circuit, a first operand of the computation circuit as a current that equals to a product of the first operand and a reference unit current;   converting, by a time multiplier circuit, a second operand of said computation circuit as a duration that equals to a product of the second operand and a reference unit time period; and   generating a charge based on the current and the duration.   
     
     
         33 . The method of  claim 32 , wherein converting a first operand of the computation circuit as a current comprises:
 connecting a plurality of current mirrors in parallel, and in each current mirror in said plurality of current mirrors, producing an output current.   
     
     
         34 . The method of  claim 33 , further comprising:
 controlling a drive strength of each of said current mirrors.   
     
     
         35 . The method of  claim 32 , wherein converting said second operand of said computation circuit comprises counting said reference unit. 
     
     
         36 . The method of  claim 35 , wherein said magnitude to time converter circuit further comprises a plurality of toggle flip-flops connected in series, and a reset circuit configured to reset said counter circuit. 
     
     
         37 . The method of  claim 32 , wherein converting said first operand of the computation circuit as a current further comprises:
 for a bit in the second operand;   producing a multiplied reference current based on said reference unit current and a magnitude represented by said second operand; and   counting, by a magnitude to time converter circuit, said multiplied reference current.   
     
     
         38 . The method of  claim 31 , wherein aggregating said plurality of charges from said plurality of computation circuits further comprises:
 for each product pair in said plurality of product pairs; and   adding charges to a charge accumulating circuit and drawing charges from said charge accumulating circuit.   
     
     
         39 . The method of  claim 38 , wherein adding charges to a charge accumulating circuit comprises:
 coupling a charging switch to a capacitor; and   controlling said charging switch and charging said capacitor in response to a sign bit of said first operand and a sign bit of said second operand being the same.   
     
     
         40 . The method of  claim 38 , wherein adding charges to a charge accumulating circuit comprises:
 coupling a charging switch to the capacitor; and   controlling said discharging switch and discharging said capacitor in response to a sign bit of said first operand and a sign bit of said second operand being different.

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