Integrated circuit structures with contoured interconnects

Abstract

Integrated circuit (IC) structures include transistor devices with interconnect structures, e.g., a source contact, drain contact, and/or gate contact. The interconnect structures have rounded top surfaces. Contouring the top surfaces of transistor contacts may decrease the likelihood of electrical shorting and may permit a larger volume of insulating dielectric between adjacent contacts.

1 . An integrated circuit (IC) package, comprising:
 a package substrate; and   an IC die coupled to the package substrate including:
 a first interconnect, 
 a second interconnect, 
 a third interconnect, wherein the third interconnect is between the first interconnect and the second interconnect, and the first interconnect and the second interconnect have top surfaces, and 
 a base structure, wherein the first interconnect has a base structure-facing surface between the base structure and the top surface of the first interconnect, the second interconnect has a base structure-facing surface between the base structure and the top surface of the second interconnect, and a distance between the first interconnect and the second interconnect, proximate to the top surfaces of the first and second interconnects, is greater than a distance between the first interconnect and the second interconnect proximate to the base structure-facing surfaces of the first and second interconnects. 
   
     
     
         2 . The IC package of  claim 1 , further comprising:
 first spacer material between the first interconnect and the third interconnect; and   second spacer material between the second interconnect and the third interconnect.   
     
     
         3 . The IC package of  claim 2 , wherein the first interconnect includes a first metal, a width of the first metal has a first value, and a thickness of the first spacer material is between 10% of the first value and 30% of the first value. 
     
     
         4 . The IC package of  claim 2 , wherein the first spacer material extends at least partially onto the top surface of the first interconnect. 
     
     
         5 . The IC package of  claim 2 , wherein the second spacer material extends at least partially onto the top surface of the second interconnect. 
     
     
         6 . The IC package of  claim 1 , wherein the base structure includes a semiconductor fin. 
     
     
         7 . The IC package of  claim 1 , wherein the base structure includes a semiconductor nanowire. 
     
     
         8 . The IC package of  claim 1 , wherein the base structure includes at least a portion of a metallization stack. 
     
     
         9 . The IC package of  claim 8 , wherein the first and second interconnects are source/drain (S/D) contacts. 
     
     
         10 . The IC package of  claim 1 , wherein the first and second interconnects are gate contacts. 
     
     
         11 . The IC package of  claim 1 , wherein the first interconnect comprises a first metal and a first liner material. 
     
     
         12 . The IC package of  claim 11 , wherein the first liner material is recessed below the top surface of the first interconnect. 
     
     
         13 . The IC package of  claim 12 , wherein the second interconnect comprises a second metal and a second liner material, and the second liner material is recessed below the top surface of the second interconnect. 
     
     
         14 . The IC package of  claim 11 , wherein the first liner material comprises titanium and nitrogen. 
     
     
         15 . The IC package of  claim 1 , further comprising: further comprising:
 a first via in conductive contact with the first interconnect;   a second via in conductive contact with the second interconnect; and   a third via in conductive contact with the third interconnect.   
     
     
         16 . The IC package of  claim 15 , wherein the first via comprises a liner material and a fill metal, and the liner material is in contact with a first metal of the first interconnect. 
     
     
         17 . The IC package of  claim 16 , wherein the liner material is in contact with spacer material, and the spacer material is at least partially between the first interconnect and the third interconnect. 
     
     
         18 . The IC package of  claim 1 , further comprising conductive contacts at a surface of the IC die. 
     
     
         19 . The IC package of  claim 18 , further comprising solder resist proximate to the conductive contacts. 
     
     
         20 . The IC package of  claim 1 , wherein the first interconnect, the second interconnect, and the third interconnect are in a device region of the IC die.