Semiconductor chip devices and methods for polynucleotide synthesis

Abstract

Systems and methods for polynucleotide synthesis utilize electrochemical deprotection and novel redox chemistries compatible with advanced CMOS nodes, for highly reliable and massively scalable parallel construction of polynucleotide segments having a desired sequence or sequences. Via use of these exemplary techniques, low-cost and large-scale polynucleotide synthesis is facilitated, for example for data storage and retrieval applications.

1 . (canceled) 
     
     
         2 . A method for modulating pH on a CMOS chip in an addressable, voltage-directed manner, the method comprising:
 applying a first solution to a first set of electrodes of the CMOS chip; and   applying a voltage to the first set of electrodes that modulates the localized pH of the first solution.   
     
     
         3 . The method of  claim 2 , wherein the first solution comprises acetonitrile. 
     
     
         4 . The method of  claim 2 , wherein the first solution comprises two components. 
     
     
         5 . The method of  claim 4 , wherein the two components comprise a first quinone and a second quinone. 
     
     
         6 . The method of  claim 5 , wherein the ratio of the first quinone to the second quinone is greater than 2. 
     
     
         7 . The method of  claim 2 , wherein the first solution comprises three components. 
     
     
         8 . The method of  claim 7 , wherein the first solution comprises a first quinone, a second quinone, and acetonitrile. 
     
     
         9 . The method of  claim 2 , wherein the voltage applied is less than about 1.5V. 
     
     
         10 . The method of  claim 2 , wherein the voltage applied is about 0.9V. 
     
     
         11 . The method of  claim 2 , wherein the voltage is modulated. 
     
     
         12 . The method of  claim 11 , wherein the voltage is modulated in time. 
     
     
         13 . The method of  claim 2 , further comprising synthesizing polynucleotides on the CMOS chip. 
     
     
         14 . The method of  claim 13 , wherein synthesizing polynucleotides comprises a step of:
 removing a protecting group on the CMOS chip.   
     
     
         15 . The method of  claim 14 , wherein synthesizing polynucleotides further comprises steps of:
 providing, on or adjacent to the first set of electrodes, a polynucleotide synthesis region functionalized to support polynucleotide synthesis;   identifying a target nucleotide to be incorporated;   applying a voltage to the first set of electrodes to drive acid generation for deprotection; and   providing a desired monomer in either the first solution or a second solution.   
     
     
         16 . The method of  claim 15 , wherein the polynucleotide synthesis region is planar. 
     
     
         17 . The method of  claim 16 , further comprising:
 providing a second set of electrodes that surround the first set of electrodes in a planar manner.   
     
     
         18 . The method of  claim 15 , wherein the electrodes and synthesis regions are arranged as an array with a pitch selected from the group consisting of less than 30 microns, less than 10 microns, and less than 1 micron. 
     
     
         19 . The method of  claim 15 , wherein a plurality of polynucleotide synthesis steps are performed until a target polynucleotide sequence is generated. 
     
     
         20 . The method of  claim 19 , wherein at least a portion of the target polynucleotide sequence contains error correction sequence elements. 
     
     
         21 . The method of  claim 19 , wherein at least a portion of a target polynucleotide sequence population comprises a consensus error corrected sequence.