Power regulation circuit and method for chip

Abstract

Provided are a power regulation circuit and method for a chip, and a power supply circuit for a circuit. The power regulation circuit includes an LC circuit and an LC correction circuit. One terminal of the LC circuit is electrically connected to a positive pole of a chip and a positive electrode of a power supply. The other terminal of the LC circuit is electrically connected to a negative pole of the chip and a negative pole of the power supply. The LC correction circuit is electrically connected to the chip and the LC circuit, and is used to regulate a working parameter of the LC circuit according to the current working mode of the chip.

What is claimed is: 
     
         1 . A power regulation circuit for a chip, comprising:
 an LC circuit, wherein one terminal of the LC circuit is electrically connected to each of a positive pole of the chip and a positive pole of a power supply, and the other terminal of the LC circuit is electrically connected to each of a negative pole of the chip and a negative pole of the power supply; and   an LC correction circuit, wherein the LC correction circuit is electrically connected to each of the chip and the LC circuit, and is configured to adjust a working parameter of the LC circuit according a current working mode of the chip.   
     
     
         2 . The power regulation circuit for a chip of  claim 1 , wherein the LC correction circuit is configured to determine a current clock signal of the chip, according to the current working mode of the chip; and adjust the working parameter of the LC circuit according to the current clock signal of the chip. 
     
     
         3 . The power regulation circuit for a chip of  claim 2 , wherein the LC correction circuit is configured to determine a working frequency of the chip according to the current clock signal of the chip; and adjust a resonant frequency of the LC circuit according to the working frequency of the chip. 
     
     
         4 . The power regulation circuit for a chip of  claim 1 , wherein the LC circuit comprises an adjustable capacitor and an adjustable inductor connected in series with each other,
 one terminal of a series circuit constituted by the adjustable capacitor and the adjustable inductor is electrically connected to each of the positive pole of the chip and the positive pole of the power supply, and the other terminal of the series circuit constituted by the adjustable capacitor and the adjustable inductor is electrically connected to each of the negative pole of the chip and the negative pole of the power supply; and   the LC correction circuit is electrically connected to each of the adjustable capacitor and the adjustable inductor, and is configured to adjust, according to the current working mode of the chip, an inductance value of the adjustable inductor and a capacitance value of the adjustable capacitor, to make a resonant frequency of the LC circuit match the current working mode of the chip.   
     
     
         5 . The power regulation circuit for a chip of  claim 1 , further comprising:
 an adjustable resistor connected in series with the LC circuit, wherein one terminal of a series circuit constituted by the adjustable resistor and the LC circuit is electrically connected to the positive pole of the chip and the positive pole of the power supply, and the other terminal of the series circuit constituted by the adjustable resistor and the LC circuit is electrically connected to each of the negative pole of the chip and the negative pole of the power supply; and   an impedance configuration circuit, wherein the impedance configuration circuit is electrically connected to each of the chip and the adjustable resistor, and is configured to adjust a resistance value of the adjustable resistor according to the current working mode of the chip.   
     
     
         6 . The power regulation circuit for a chip of  claim 5 , wherein the impedance configuration circuit is further configured to acquire a current of the chip in the current working mode and a rated voltage of the chip; and adjust the resistance value of the adjustable resistor, according to the rated voltage and the current, wherein a product of the adjusted resistance value and the current matches the rated voltage. 
     
     
         7 . The power regulation circuit for a chip of  claim 6 , wherein the impedance configuration circuit is further is configured to determine that the product of the adjusted resistance value and the current matches the rated voltage and stop adjustment of the adjustable resistor, when it is detected that an absolute value of a difference between the rated voltage and the product of the adjusted resistance value and the current does not exceed a specified value. 
     
     
         8 . The power regulation circuit for a chip of  claim 5 , wherein the LC correction circuit is further configured to receive an enabling signal output by the chip; and control a working state of the LC correction circuit according to the enabling signal; and
 the impedance configuration circuit is further configured to receive the enabling signal output by the chip; and control a working state of the impedance configuration circuit according to the enabling signal.   
     
     
         9 . A power regulation method for a chip, wherein the method is implemented by a power regulation circuit for a chip, the power regulation circuit comprises an LC circuit and an LC correction circuit, one terminal of the LC circuit is electrically connected to each of a positive pole of the chip and a positive pole of a power supply, and the other terminal of the LC circuit is electrically connected to each of a negative pole of the chip and a negative pole of the power supply, the LC correction circuit is electrically connected to each of the chip and the LC circuit, and the method comprises:
 acquiring, by the LC correction circuit, a current working mode of the chip; and   adjusting, by the LC correction circuit, a working parameter of the LC circuit according to the current working mode of the chip.   
     
     
         10 . The power regulation method for a chip of  claim 9 , wherein the adjusting a working parameter of the LC circuit according to the current working mode of the chip, comprises:
 determining a current clock signal of the chip, according to the current working mode of the chip; and   adjusting the working parameter of the LC circuit, according to the current clock signal.   
     
     
         11 . The power regulation method for a chip of  claim 9 , wherein the adjusting a working parameter of the LC circuit according to the current working mode of the chip, comprises:
 determining a working frequency of the chip, according to the current clock signal of the chip; and   adjusting the working parameter of the LC circuit according to the working frequency of the chip.   
     
     
         12 . The power regulation method for a chip of  claim 10 , wherein the LC circuit comprises an adjustable capacitor and an adjustable inductor connected in series with each other, the adjusting a working parameter of the LC circuit according to the current working mode, comprises:
 adjusting, according to the current clock signal, an inductance value of the adjustable inductor and a capacitance value of the adjustable capacitor, to adjust a resonant frequency of the LC circuit, wherein the adjusted resonant frequency matches the current clock signal.   
     
     
         13 . The power regulation method for a chip of  claim 9 , wherein the power regulation circuit for a chip further comprises an adjustable resistor and an impedance configuration circuit, the adjustable resistor is connected in series with the LC circuit, and the impedance configuration circuit is electrically connected to each of the chip and the adjustable resistor, the method further comprises:
 adjusting, by the impedance configuration circuit, a resistance value of the adjustable resistor according to the current working mode of the chip.   
     
     
         14 . The power regulation method for a chip of  claim 13 , wherein the adjusting a resistance value of the adjustable resistor according to the current working mode of the chip, comprises:
 acquiring a current of the chip in the current working mode and a rated voltage of the chip; and   adjusting the resistance value of the adjustable resistor, according to the rated voltage and the current, wherein a product of the adjusted resistance value and the current matches the rated voltage.   
     
     
         15 . The power regulation method for a chip of  claim 14 , wherein the adjusting the resistance value of the adjustable resistor according to the rated voltage and the current, comprises:
 in response to detecting that an absolute value of a difference between the rated voltage and the product of the adjusted resistance value and the current does not exceed a specified value, determining that the product of the adjusted resistance value and the current matches the rated voltage, and stopping adjustment of the adjustable resistor.   
     
     
         16 . The power regulation method for a chip of  claim 13 , further comprising:
 receiving an enabling signal output by the chip; and   controlling, according to the enabling signal, working states of the impedance configuration circuit and the LC correction circuit.   
     
     
         17 . A power supply circuit for a chip, comprising:
 a power supply;   an LC circuit, wherein one terminal of the LC circuit is electrically connected to each of a positive pole of the chip and a positive pole of the power supply, and the other terminal of the LC circuit is electrically connected to each of a negative pole of the chip and a negative pole of the power supply; and   an LC correction circuit, wherein the LC correction circuit is electrically connected to each of the chip and the LC circuit, and is configured to adjust a working parameter of the LC circuit according a current working mode of the chip.   
     
     
         18 . The power supply circuit for a chip of  claim 17 , wherein the LC circuit comprises an adjustable capacitor and an adjustable inductor connected in series with each other,
 one terminal of the adjustable capacitor is connected with one terminal of the adjustable inductor, the other terminal of the adjustable capacitor is electrically connected to each of the positive pole of the chip and the positive pole of the power supply, and the other terminal of the adjustable inductor is electrically connected to each of the negative pole of the chip and the negative pole of the power supply; and   the LC correction circuit is electrically connected to each of the adjustable capacitor and the adjustable inductor, and is configured to adjust, according to the current working mode of the chip, an inductance value of the adjustable inductor and a capacitance value of the adjustable capacitor, to make a resonant frequency of the LC circuit match the current working mode of the chip.   
     
     
         19 . The power supply circuit for a chip of  claim 17 , further comprising:
 an adjustable resistor, wherein one terminal of the adjustable resistor is connected with one terminal of the LC circuit, the other terminal of the adjustable resistor is electrically connected to the positive pole of the chip and the positive pole of the power supply, and the other terminal of and the LC circuit is electrically connected to each of the negative pole of the chip and the negative pole of the power supply; and   an impedance configuration circuit, wherein the impedance configuration circuit is electrically connected to each of the chip and the adjustable resistor, and is configured to adjust a resistance value of the adjustable resistor according to the current working mode of the chip.   
     
     
         20 . The power supply circuit for a chip of  claim 17 , further comprising:
 an on-chip decoupling capacitor, wherein a first terminal of the on-chip decoupling capacitor is electrically connected to each of the positive pole of the power supply and the positive pole of the chip, and a second terminal of on-chip decoupling capacitor is electrically connected to each of the negative pole of the power supply and the negative pole of the chip; and   two parasitic inductors, wherein one of the two parasitic inductors is connected in series between an the on-chip decoupling capacitor and the positive pole of the power supply, and the other one of the two parasitic inductors is connected in series between the on-chip decoupling capacitor and the negative pole of the power supply.