Multistage micromechanical timepiece and method for making same

Abstract

A micromechanical timepiece, and a method for making the same, having a plurality of mutually secured functional sub-assemblies stacked in a direction (Z) to form a multistage assembly, wherein each functional sub-assembly comprises a single semiconductor material and is secured to another sub-assembly via bridges made of the semiconductor material, and in that at least one sub-assembly comprises at least two portions, the portions being movable relative to each other and relative to another sub-assembly to which at least one of the portions is secured via at least one deformable link integrally formed between the portions.

What is claimed: 
     
         1 . A method for manufacturing a timepiece according to includes the following successive steps:
 a. Providing a substrate of a semiconductor material, said substrate preferably comprising alignment markers on a first face, and   b. Depositing, on a second face of the substrate, a sacrificial material layer of a determined height h and homogeneous over the entire area of the second face of the substrate;   c. Structuring the sacrificial material layer by an etching process to form openings therein over its entire height h;   d. Depositing a growth layer of a semiconductor material on the sacrificial material layer so as to fill the previously formed openings and completely cover it,   e. Structuring the growth layer by an etching process to form a first functional subassembly including portions movable relative to each other and to the substrate by means of at least one deformable link;   f. Structuring the semiconductor material substrate by an etching process to form a second functional subassembly including portions movable relative to each other and to the growth layer by means of at least a deformable link;   g. Removing the sacrificial material layer between the substrate and the growth layer to form linking bridges between said subassemblies and release said timepiece.   
     
     
         2 . The method according to  claim 1 , wherein steps e) and f) include the implementation of a reactive ion etching process. 
     
     
         3 . The method according to  claim 2 , including a surface flattening step after steps b) and/or d). 
     
     
         4 . The method according to  claim 1 , the substrate and the growth layer being formed of the same semiconductor material, in particular silicon (Si). 
     
     
         5 . The method according to  claim 1 , the substrate and the growth layer being formed of the same doped semi-conductor. 
     
     
         6 . The method according to  claim 1 , the growth layer being formed by growth of silicon on the substrate in the openings formed in the sacrificial material layer. 
     
     
         7 . The method according to  claim 1 , including a step of coating the subassemblies or a part thereof by a functionalization layer. 
     
     
         8 . The method according to  claim 1 , wherein steps b) to e) are repeated n times, n being an integer between 1 and 5, prior to or after step f). 
     
     
         9 . The method according to  claim 1 , wherein steps b) to e) are reproduced n times, n being an integer between 1 and 5, on both faces of the substrate.