Method and Apparatus for Configuring a Reduced Instruction Set Computer Processor Architecture to Execute a Fully Homomorphic Encryption Algorithm

Abstract

Systems and methods for configuring a reduced instruction set computer processor architecture to execute fully homomorphic encryption (FHE) logic gates as a streaming topology. The method includes parsing sequential FHE logic gate code, transforming the FHE logic gate code into a set of code modules that each have in input and an output that is a function of the input and which do not pass control to other functions, creating a node wrapper around each code module, configuring at least one of the primary processing cores to implement the logic element equivalents of each element in a manner which operates in a streaming mode wherein data streams out of corresponding arithmetic logic units into the main memory and other ones of the plurality arithmetic logic units.

What is claimed is: 
     
         1 . A method for configuring a reduced instruction set computer processor architecture to process a Discrete Fourier Transform (DFT) of a finite-length sequence N, wherein the computer processor architecture includes a plurality of primary processing cores defined by RISC processors, each primary processing core comprising a main memory, at least one cache memory, and a plurality of arithmetic logic units, each primary core having an associated node wrapper, the node wrapper including access memory associated with each arithmetic logic unit, a load/unload matrix associated with each arithmetic logic unit, the method comprising:
 (a) applying a Decimation-in-Frequency algorithm to the DFT to decompose the DFT of a finite-length sequence N into two derived DFTs each of a length N/2;   (b) constructing a logic element equivalent of each stage of the derived DFTs in which inputs and outputs are composed of real and imaginary components;   (c) repeating (a) and (b) for each stage of the DFT except for the endpoint stages of the DFT;   (d) for each endpoint stage of the DFT constructing a logic element equivalent of the corresponding stage of the derived DFTs in which inputs and outputs are composed of only real components;   (e) configuring at least one primary core of the computer processor architecture to implement the logic element equivalents of each stage of the DFTs in a manner which operates in a streaming mode wherein data streams out of corresponding arithmetic logic units into the main memory and other ones of the plurality arithmetic logic units; and   (f) configuring the computer processor architecture to couple the output of each stage on the DFT to the input of a subsequent stage.   
     
     
         2 . The method of  claim 1 , wherein the logic of each stage includes multiple butterfly operations. 
     
     
         3 . The method of  claim 2 , wherein step (b) comprises configuring a butterfly operation so that a first input/output is for the real part and a second input/output are for the imagery part and the input/output is interleaved as p and q, wherein p and q inputs of the butterfly operation are selected from different addresses within the input buffer at different stages. 
     
     
         4 . The method of  claim 3 , wherein “add”, “subtraction” and “multiply” logic elements are used to calculate real and imagery parts of the multiplication of complex inputs and the complex constant “w”. 
     
     
         5 . A method for configuring a reduced instruction set computer processor architecture to execute a fully homomorphic encryption (FHE) logic gate as a streaming topology, wherein the computer processor architecture includes a plurality of primary processing cores defined by RISC processors, each primary processing core comprising a main memory, at least one cache memory, and a plurality of arithmetic logic units, each primary core having an associated node wrapper, the node wrapper including access memory associated with each arithmetic logic unit, a load/unload matrix associated with each arithmetic logic unit, the method comprising:
 parsing sequential FHE logic gate code;   transforming the FHE logic gate code into a set of code modules that each have in input and an output that is a function of the input and which do not pass control to other functions;   creating a node wrapper around each code module;   configuring at least one of the primary processing cores to implement the logic element equivalents of each element in a manner which operates in a streaming mode wherein data streams out of corresponding arithmetic logic units into the main memory and other ones of the plurality arithmetic logic units.   
     
     
         6 . The method of  claim 5 , wherein the transforming comprises:
 locating a pointer in the FHE logic gate code;   backtracking through the code to find data that was created and the allocated block of data that is pointed to by the pointer;   determining the size of the allocated block;   replacing the pointer with a data array corresponding to the allocated block; and using the array as streaming data.   
     
     
         7 . A computer processor architecture for processing a Discrete Fourier Transform (DFT) of a finite-length sequence N, the computer processor architecture comprising:
 a plurality of primary processing cores defined by RISC processors, each primary processing core comprising a main memory, at least one cache memory, and a plurality of arithmetic logic units, each primary core having an associated node wrapper, the node wrapper including access memory associated with each arithmetic logic unit, a load/unload matrix associated with each arithmetic logic unit;   wherein multiple stages of the DFT are constructed by, (a) applying a Decimation-in-Frequency algorithm to the DFT to decompose the DFT of a finite-length sequence N into two derived DFTs each of a length N/2, (b) constructing a logic element equivalent of each stage of the derived DFTs in which inputs and outputs are composed of real and imaginary components, (c) repeating (a) and (b) for each stage of the DFT except for the endpoint stages of the DFT, (d) for each endpoint stage of the DFT constructing a logic element equivalent of the corresponding stage of the derived DFTs in which inputs and outputs are composed of only real components;   wherein at least one primary core of the computer processor architecture is configured to implement the logic element equivalents of each stage of the DFTs in a manner which operates in a streaming mode wherein data streams out of corresponding arithmetic logic units into the main memory and other ones of the plurality arithmetic logic units; and   wherein the computer processor architecture is configured to couple the output of each stage on the DFT to the input of a subsequent stage.   
     
     
         8 . The architecture of  claim 7 , wherein the logic of each stage includes multiple butterfly operations. 
     
     
         9 . The architecture of  claim 8 , wherein (b) comprises configuring a butterfly operation so that a first input/output is for the real part and a second input/output are for the imagery part and the input/output is interleaved as p and q, wherein p and q inputs of the butterfly operation are selected from different addresses within the input buffer at different stages. 
     
     
         10 . The architecture of  claim 9 , wherein “add”, “subtraction” and “multiply” logic elements are used to calculate real and imagery parts of the multiplication of complex inputs and the complex constant “w”. 
     
     
         11 . A computer processor architecture for executing a fully homomorphic encryption (FHE) logic gate as a streaming topology, the computer processor architecture comprising:
 a plurality of primary processing cores defined by RISC processors, each primary processing core comprising a main memory, at least one cache memory, and a plurality of arithmetic logic units, each primary core having an associated node wrapper, the node wrapper including access memory associated with each arithmetic logic unit, a load/unload matrix associated with each arithmetic logic unit;   wherein the sequential FHE logic gate code has been transformed into a set of code modules that each have an input and an output that is a function of the input and which do not pass control to other functions, a node wrapper has been created around each code module; and   wherein at least one of the primary processing cores has been configured architecture to implement the logic element equivalents of each element in a manner which operates in a streaming mode wherein data streams out of corresponding arithmetic logic units into the main memory and other ones of the plurality arithmetic logic units.   
     
     
         12 . The architecture of  claim 11 , wherein the logic gate code was transformed by locating a pointer in the FHE logic gate code, backtracking through the code to find data that was created and the allocated block of data that is pointed to by the pointer, determining the size of the allocated block, replacing the pointer with a data array corresponding to the allocated block, and using the array as streaming data.