Interface Circuit

Abstract

An interface circuit includes a phase inverter. An input end of the phase inverter is connected to a signal output end of a first power domain circuit, and an output end of the phase inverter is connected to a signal input end of a second power domain circuit. A power end of the phase inverter is connected to a power supply of the first power domain circuit, and a ground end of the phase inverter is connected to a reference ground of the second power domain circuit. Alternatively, a power end of the phase inverter is connected to a power supply of the second power domain circuit, and a ground end of the phase inverter is connected to a reference ground of the first power domain circuit.

1 . An interface circuit comprising:
 a first power domain circuit comprising:
 a first signal output end; 
 a first power supply; and 
 a first reference ground; 
   a second power domain circuit comprising:
 a second signal output end; 
 a second power supply; and 
 a second reference ground; 
   a target power domain circuit comprising:
 a target reference ground; 
 a target power supply; and 
 a target signal input end; and 
   a NAND gate circuit comprising:
 a first power end coupled to the first power supply; 
 a second power end coupled to the second power supply; 
 a first input end corresponding to the first power end and coupled to the first signal output end; 
 a second input end corresponding to the second power end and coupled to the second signal output end; 
 a ground end coupled to the target reference ground; and 
 an output end coupled to the target signal input end. 
   
     
     
         2 . The interface circuit of  claim 1 , wherein the NAND gate circuit further comprises a plurality of p-channel metal-oxide semiconductors (PMOS) transistors comprising a plurality of gates, a plurality of drains, and a plurality of sources, wherein each of the gates is coupled to one of the first signal output end or the second signal output end, wherein the drains are coupled to the target signal input end, and wherein the sources are coupled to one of the first power supply or the second power supply. 
     
     
         3 . The interface circuit of  claim 1 , wherein the NAND gate circuit further comprises a plurality of n-channel metal-oxide semiconductor (NMOS) transistors comprising a plurality of gates, a plurality of drains, and a plurality of sources, wherein each of the gates is coupled to one of the first signal output end or the second signal output end, wherein the drain of a first NMOS transistor of the plurality of NMOS transistors is coupled to the target signal input end, wherein the source of a second NMOS transistor of the plurality of NMOS transistors is coupled to the target reference ground, and wherein the plurality of NMOS transistors are connected in series. 
     
     
         4 . The interface circuit of  claim 1 , wherein the NAND gate circuit is configured to transition between logical states of a signal. 
     
     
         5 . The interface circuit of  claim 4 , wherein the NAND gate circuit is further configured to output a signal at a logical low level when an input signal is at a logical high level. 
     
     
         6 . The interface circuit of  claim 4 , wherein the NAND gate circuit is further configured to output a signal at a logical high level when an input signal is at a logical low level. 
     
     
         7 . An interface circuit comprising:
 a first power domain circuit comprising:
 a first signal output end; 
 a first power supply; and 
 a first reference ground; 
   a second power domain circuit comprising:
 a second signal output end; 
 a second power supply; and 
 a second reference ground; 
   a target power domain circuit comprising:
 a target reference ground; 
 a target power supply; and 
 a target signal input end; and 
   a NAND gate circuit comprising:
 a first power end coupled to the target power supply; 
 a second power end coupled to the target power supply; 
 a first input end corresponding to the first power end and coupled to the first signal output end; 
 a second input end corresponding to the second power end and coupled to the second signal output end; 
 a ground end coupled to the second reference ground; and 
 an output end coupled to the target signal input end. 
   
     
     
         8 . The interface circuit of  claim 7 , wherein the NAND gate circuit further comprises a plurality of p-channel metal-oxide semiconductor (PMOS) transistors comprising a plurality of gates, a plurality of drains, and a plurality of sources, wherein each of the gates is coupled to one of the first signal output end or the second signal output end, wherein each of the drains are coupled to the target signal input end, and wherein each of the sources is coupled to target power supply. 
     
     
         9 . The interface circuit of  claim 7 , wherein the NAND gate circuit further comprises a plurality of n-channel metal-oxide semiconductor (NMOS) transistors comprising a plurality of gates, a plurality of drains, and a plurality of sources, wherein each of the gates is coupled to one of the first signal output end or the second signal output end, wherein the drain of a first NMOS transistor of the plurality of NMOS transistors is coupled to the target signal input end, wherein the source of a second NMOS transistor of the plurality of NMOS transistors is coupled to the second reference ground, and wherein the plurality of NMOS transistors are connected in series. 
     
     
         10 . The interface circuit of  claim 7  wherein the NAND gate circuit is configured to transition between logical states of a signal. 
     
     
         11 . The interface circuit of  claim 10 , wherein the NAND gate circuit is further configured to output a signal at a logical low level when an input signal is at a logical high level. 
     
     
         12 . The interface circuit of  claim 10 , wherein the NAND gate circuit is further configured to output a signal at a logical high level when an input signal is at a logical low level. 
     
     
         13 . An interface circuit comprising:
 a NOR gate circuit comprising:
 a plurality of ground ends configured to couple to a target reference ground of a target power domain circuit; 
 a plurality of input ends coupled to a plurality of signal output ends of a plurality of power domain circuits, wherein each of the input ends corresponds with each of the ground ends, and wherein the input ends comprise a target input end; 
 an output end coupled to a target signal input end of the target power domain circuit; and 
 a power end coupled to a power supply of a power domain circuit, wherein the power domain circuit comprises a target signal output end of the signal output ends, wherein the target signal output end is coupled to the target input end, or the power end is configured to couple to a power supply of the target power domain circuit, wherein one of the ground ends is configured to couple to a reference ground of a power domain circuit to which a signal output end of the signal output ends belongs. 
   
     
     
         14 . The interface circuit of  claim 13 , wherein the NOR gate circuit further comprises a plurality of p-channel metal-oxide semiconductors (PMOS) transistors comprising a plurality of gates, a plurality of drains, and a plurality of sources, wherein the gates of the plurality of PMOS transistors is coupled to one of the plurality of signal output ends, wherein one of the drains of one of the plurality of PMOS transistors is coupled to the target signal input end, wherein the source of a first PMOS transistor of the plurality of PMOS transistors is coupled to the power supply of the power domain circuit to which the target signal output end belongs, wherein the plurality of PMOS transistors are coupled in series. 
     
     
         15 . The interface circuit of  claim 13 , wherein the NOR gate circuit further comprises a plurality of p-channel metal-oxide semiconductor (PMOS) transistors comprising a plurality of gates, a plurality of drains, and a plurality of sources, wherein the gates of the plurality of PMOS transistors is coupled to one of the plurality of signal output ends, wherein one of the drains of one of the plurality of PMOS transistors is coupled to the target signal input end, wherein the source of a first PMOS transistor of the plurality of PMOS transistors is coupled to the power supply of the target power domain circuit, and wherein the plurality of PMOS transistors are coupled in series. 
     
     
         16 . The interface circuit of  claim 13 , wherein the NOR gate circuit further comprises and n-channel metal-oxide semiconductor NMOS transistors comprising a plurality of gates, a plurality of drains, and a plurality of sources, wherein the gates of the plurality of PMOS transistors is coupled to one of the plurality of signal output ends, wherein each of the drains are coupled to the target signal input end, wherein each of the sources are coupled to the target reference ground. 
     
     
         17 . The interface circuit of  claim 13 , wherein the NOR gate circuit further comprises n-channel metal-oxide semiconductor (NMOS) transistors comprising a plurality of gates, a plurality of drains, and a plurality of sources, wherein the gates of the plurality of PMOS transistors is coupled to one of the plurality of signal output ends, wherein each of the drains are coupled to the target signal input end, wherein one of the sources of one of the plurality of NMOS transistors is coupled to the reference ground of the power domain circuit to which the signal output end belongs. 
     
     
         18 . The interface circuit of  claim 13 , wherein the NOR gate circuit is configured to transition between logical states of a signal. 
     
     
         19 . The interface circuit of  claim 18 , wherein the NOR gate circuit is further configured to output a signal at a logical low level when an input signal is at a logical high level. 
     
     
         20 . The interface circuit of  claim 18 , wherein the NOR gate circuit is further configured to output a signal at a logical high level when an input signal is at a logical low level.