Apparatus, systems, and methods for providing computational imaging pipeline

Abstract

The present application relates generally to a parallel processing device. The parallel processing device can include a plurality of processing elements, a memory subsystem, and an interconnect system. The memory subsystem can include a plurality of memory slices, at least one of which is associated with one of the plurality of processing elements and comprises a plurality of random access memory (RAM) tiles, each tile having individual read and write ports. The interconnect system is configured to couple the plurality of processing elements and the memory subsystem. The interconnect system includes a local interconnect and a global interconnect.

We claim: 
     
         1 - 20 . (canceled) 
     
     
         21 . A memory comprising first instructions to cause programmable circuitry of a device to at least:
 assign a first node of a flow graph to first processor circuitry based on a first burden associated with a first operation of the first node, the flow graph representative of operations;   assign a second node of the flow graph to second processor circuitry based on a second burden associated with a second operation of the second node; and   deploy second instructions associated with the first operation to the first processor circuitry and third instructions associated with the second operation to the second processor circuitry, the flow graph including an edge representative of a relationship between the first node and the second node.   
     
     
         22 . The memory of  claim 21 , wherein the device is a first device, the first processor circuitry includes a first graphics processing unit (GPU) of a second device, and the second processor circuitry includes a second GPU of the second device. 
     
     
         23 . The memory of  claim 21 , wherein the device is a first device, the first processor circuitry includes a graphics processing unit of a second device, and the second processor circuitry includes a central processing unit of the second device. 
     
     
         24 . The memory of  claim 21 , wherein the memory is first memory, and the first instructions are to cause the programmable circuitry to assign the first node to the first processor circuitry based on performance information associated with second memory. 
     
     
         25 . The memory of  claim 21 , wherein the flow graph includes a third node, and the first instructions are to cause the programmable circuitry to, based on a third burden associated with a third operation of the third node, assign a first portion of the third node to the first processor circuitry and assign a second portion of the third node to the second processor circuitry. 
     
     
         26 . The memory of  claim 21 , wherein the flow graph includes a third node and a fourth node, and the first instructions are to cause the programmable circuitry to fuse the third node and the fourth node into a fifth node. 
     
     
         27 . The memory of  claim 26 , wherein the device is a first device, and the first instructions are to cause the programmable circuitry to assign the fifth node to the first processor circuitry of a second device. 
     
     
         28 . The memory of  claim 21 , wherein the first burden is associated with memory usage for the first operation. 
     
     
         29 . A first device comprising:
 memory;   first instructions; and   programmable circuitry to cooperate with the first instructions to:
 assign a first node of a flow graph to first processor circuitry based on a first burden of a first operation of the first node, the flow graph representative of operations; 
 assign a second node of the flow graph to second processor circuitry based on a second burden of a second operation of the second node; and 
 deploy second instructions associated with the first operation to the first processor circuitry and third instructions associated with the second operation to the second processor circuitry, the flow graph including an edge representative of a relationship between the first node and the second node. 
   
     
     
         30 . The first device of  claim 29 , wherein the first processor circuitry includes a first graphics processing unit (GPU) of a second device, and the second processor circuitry includes a second GPU of the second device. 
     
     
         31 . The first device of  claim 29 , wherein the first processor circuitry includes a graphics processing unit of a second device, and the second processor circuitry includes a central processing unit of the second device. 
     
     
         32 . The first device of  claim 29 , wherein the memory is first memory, and the programmable circuitry is to assign the first node to the first processor circuitry based on performance information associated with second memory. 
     
     
         33 . The first device of  claim 29 , wherein the flow graph includes a third node, and the programmable circuitry is to, based on a third burden of a third operation of the third node, assign a first portion of the third node to the first processor circuitry and assign a second portion of the third node to the second processor circuitry. 
     
     
         34 . The first device of  claim 29 , wherein the flow graph includes a third node and a fourth node, and the programmable circuitry is to fuse the third node and the fourth node into a fifth node. 
     
     
         35 . The first device of  claim 34 , wherein the programmable circuitry is to assign the fifth node to the first processor circuitry of a second device. 
     
     
         36 . The first device of  claim 29 , wherein the first burden is associated with memory usage for the first operation. 
     
     
         37 . A system comprising:
 first processor circuitry;   second processor circuitry;   memory;   first instructions; and   programmable circuitry associated with the first instructions to:
 assign a first node of a flow graph to the first processor circuitry based on a first burden of a first operation of the first node; 
 assign a second node of the flow graph to the second processor circuitry based on a second burden of a second operation of the second node; and 
 deploy second instructions associated with the first operation to the first processor circuitry and third instructions associated with the second operation to the second processor circuitry, the flow graph representative of operations and a relationship between the first node and the second node. 
   
     
     
         38 . The system of  claim 37 , wherein the first processor circuitry includes a first graphics processing unit (GPU), and the second processor circuitry includes a second GPU. 
     
     
         39 . The system of  claim 37 , wherein the first processor circuitry includes a graphics processing unit, and the second processor circuitry includes a central processing unit. 
     
     
         40 . The system of  claim 37 , wherein the memory is first memory, and the programmable circuitry is to assign the first node to the first processor circuitry based on performance information associated with second memory. 
     
     
         41 . The system of  claim 37 , wherein the flow graph includes a third node, and the programmable circuitry is to, based on a third burden of a third operation of the third node, assign a first portion of the third node to the first processor circuitry and assign a second portion of the third node to the second processor circuitry. 
     
     
         42 . The system of  claim 37 , wherein the flow graph includes a third node and a fourth node, and the programmable circuitry is to fuse the third node and the fourth node into a fifth node. 
     
     
         43 . The system of  claim 42 , wherein the programmable circuitry is included in a first device, and the programmable circuitry is to assign the fifth node to the first processor circuitry of a second device. 
     
     
         44 . The system of  claim 37 , wherein the first burden is associated with memory usage for the first operation.