Programming of a selected non-volatile memory cell

Abstract

In one example, a method comprises performing a first programming process on a selected non-volatile memory cell, the first programming process comprising a plurality of program-verify cycles, wherein a programming voltage duration of increasing period is applied to one of a floating gate, a control gate terminal, an erase gate terminal, and a source line terminal of the selected non-volatile memory cell in each program-verify cycle after the first program-verify cycle.

What is claimed is: 
     
         1 . A method comprising:
 performing a first programming process on a selected non-volatile memory cell, the first programming process comprising a plurality of program-verify cycles, wherein a programming voltage duration of increasing period is applied to one of a floating gate, a control gate terminal, an erase gate terminal, and a source line terminal of the selected non-volatile memory cell in each program-verify cycle after the first program-verify cycle.   
     
     
         2 . The method of  claim 1 , wherein each program-verify cycle comprises verifying that a current through the selected non-volatile memory cell during a read or verify operation is less than or equal to a first threshold current value. 
     
     
         3 . The method of  claim 1 , wherein each program-verify cycle comprises:
 applying a first voltage to one of the erase gate terminal and the control gate terminal of the selected non-volatile memory cell;   measuring a first current that results through the selected non-volatile memory cell;   applying a second voltage to the one of the erase gate terminal and the control gate terminal of the selected non-volatile memory cell;   measuring a second current that results through the selected non-volatile memory cell;   determining a slope value based on the first voltage, the second voltage, the first current, and the second current;   determining a next programming duration of the programming durations of increasing duration based on the slope value;   programming the non-volatile memory cell with the next programming duration; and   repeating the steps of determining a next programming duration and programming the non-volatile memory cell with the next programming duration until a current through the selected non-volatile memory cell during a read or verify operation is less than or equal to a first threshold current value.   
     
     
         4 . The method of  claim 1 , further comprising:
 when a current through the selected non-volatile memory cell during a read or verify operation is less than or equal to a first threshold current value, performing a second programming process until a current through the selected non-volatile memory cell during a read or verify operation is less than or equal to a second threshold current value.   
     
     
         5 . The method of  claim 1 , wherein the performing a first programming process further comprises:
 when a current through the selected non-volatile memory cell is less than or equal to a third threshold current value, erasing the selected non-volatile memory cell and repeating the first programming process.   
     
     
         6 . The method of  claim 4 , further comprising:
 performing a third programming process until a current through the selected non-volatile memory cell during a read or verify operation is less than or equal to a fourth threshold current value.   
     
     
         7 . The method of  claim 4 , wherein the second programming process comprises applying voltage pulses of increasing duration to the control gate of the selected non-volatile memory cell. 
     
     
         8 . The method of  claim 7 , wherein the second programming process further comprises applying voltage pulses of increasing duration to the erase gate of the selected non-volatile memory cell. 
     
     
         9 . The method of  claim 7 , wherein the second programming process further comprises applying voltage pulses of decreasing duration to the erase gate of the selected non-volatile memory cell. 
     
     
         10 . The method of  claim 1 , wherein the selected non-volatile memory cell is a split-gate flash memory cell. 
     
     
         11 . The method of  claim 1 , wherein the selected non-volatile memory cell is in a vector-by-matrix multiplication array in an analog neural network. 
     
     
         12 . A method comprising:
 performing a first programming process comprising multiple program-verify cycles, wherein a first programming voltage of increasing magnitude is applied to a control gate terminal of a selected non-volatile memory cell and a second programming voltage of decreasing magnitude is applied to an erase gate terminal of the selected non-volatile memory cell during the programming process, and when a current through the selected non-volatile memory cell is less than or equal to a third threshold current value, erasing the selected non-volatile memory cell and repeating the first programming process.   
     
     
         13 . A method comprising:
 performing a first programming process comprising multiple program-verify cycles, wherein a first programming voltage of increasing magnitude is applied to a control gate of a selected non-volatile memory cell and a second programming voltage of decreasing magnitude is applied to an erase gate of the selected non-volatile memory cell during the programming process;   performing a second programming process until a current through the selected non-volatile memory cell during a read or verify operation is less than or equal to a second threshold current value; and   performing a third programming process until a current through the selected non-volatile memory cell during a read or verify operation is less than or equal to a fourth threshold current value.   
     
     
         14 . A method comprising:
 performing a first programming process comprising multiple program-verify cycles, wherein a first programming voltage of increasing duration is applied to a control gate terminal of a selected non-volatile memory cell and a second programming voltage of decreasing duration is applied to an erase gate terminal of the selected non-volatile memory cell in the programming process.   
     
     
         15 . The method of  claim 14 , wherein each program-verify cycle comprises verifying that a current through the selected non-volatile memory cell during a read or verify operation is less than or equal to a first threshold current value. 
     
     
         16 . The method of  claim 14 , wherein each program-verify cycle comprises:
 applying a first voltage to one of the erase gate and the control gate of the selected non-volatile memory cell;   measuring a first current that results through the selected non-volatile memory cell;   applying a second voltage to the one of the erase gate and the control gate of the selected non-volatile memory cell;   measuring a second current that results through the selected non-volatile memory cell;   determining a slope value based on the first voltage, the second voltage, the first current, and the second current;   determining a next programming duration of the programming voltage of increasing and decreasing durations, respectively, based on the slope value;   programming the non-volatile memory cell with the next programming duration; and   repeating the steps of determining a next programming duration and programming the non-volatile memory cell with the next programming duration until a current through the selected non-volatile memory cell during a read or verify operation is less than or equal to a first threshold current value.   
     
     
         17 . The method of  claim 14 , further comprising:
 performing a second programming process until a current through the selected non-volatile memory cell during a read or verify operation is less than or equal to a second threshold current value.   
     
     
         18 . The method of  claim 14 , wherein the performing a first programming process further comprises:
 when a current through the selected non-volatile memory cell is less than or equal to a third threshold current value, erasing the selected non-volatile memory cell and repeating the first programming process.   
     
     
         19 . The method of  claim 17 , further comprising:
 performing a third programming process until a current through the selected non-volatile memory cell during a read or verify operation is less than or equal to a fourth threshold current value.   
     
     
         20 . A method comprising:
 performing a first programming process comprising multiple program-verify cycles, wherein a first programming voltage of increasing magnitude is applied to an erase gate terminal of a selected non-volatile memory cell and a second programming voltage of decreasing magnitude is applied to a control gate terminal of the selected non-volatile memory cell in the programming process.   
     
     
         21 . The method of  claim 20 , wherein each program-verify cycle comprises verifying that a current through the selected non-volatile memory cell during a read or verify operation is less than or equal to a first threshold current value. 
     
     
         22 . The method of  claim 20 , wherein each program-verify cycle comprises:
 applying a first voltage to one of the erase gate and the control gate of the selected non-volatile memory cell;   measuring a first current that results through the selected non-volatile memory cell;   applying a second voltage to the one of the erase gate and the control gate of the selected non-volatile memory cell;   measuring a second current that results through the selected non-volatile memory cell;   determining a slope value based on the first voltage, the second voltage, the first current, and the second current;   determining a next programming voltage of the programming voltages of increasing and decreasing magnitude, respectively, based on the slope value;   programming the non-volatile memory cell with the next programming voltage; and   repeating the steps of determining a next programming voltage and programming the non-volatile memory cell with the next programming voltage until a current through the selected non-volatile memory cell during a read or verify operation is less than or equal to a first threshold current value.   
     
     
         23 . The method of  claim 22 , further comprising:
 performing a second programming process until a current through the selected non-volatile memory cell during a read or verify operation is less than or equal to a second threshold current value.   
     
     
         24 . The method of  claim 22 , wherein the performing a first programming process further comprises:
 when a current through the selected non-volatile memory cell is less than or equal to a third threshold current value, erasing the selected non-volatile memory cell and repeating the first programming process.   
     
     
         25 . The method of  claim 23 , further comprising:
 performing a third programming process until a current through the selected non-volatile memory cell during a read or verify operation is less than or equal to a fourth threshold current value.   
     
     
         26 . A method comprising:
 performing a first programming operation comprising multiple program-verify cycles, wherein a first programming voltage of increasing duration is applied to an erase gate terminal of a selected non-volatile memory cell and a second programming voltage of decreasing duration is applied to a control gate terminal of the selected non-volatile memory cell in the programming operation.   
     
     
         27 . The method of  claim 26 , wherein each program-verify cycle comprises verifying that a current through the selected non-volatile memory cell during a read or verify operation is less than or equal to a first threshold current value. 
     
     
         28 . The method of  claim 27 , wherein each program-verify cycle comprises:
 applying a first voltage to one of the erase gate and the control gate of the selected non-volatile memory cell;   measuring a first current that results through the selected non-volatile memory cell;   applying a second voltage to the one of the erase gate and the control gate of the selected non-volatile memory cell;   measuring a second current that results through the selected non-volatile memory cell;   determining a slope value based on the first voltage, the second voltage, the first current, and the second current;   determining a next programming duration of the programming voltage of increasing and decreasing durations, respectively based on the slope value;   programming the non-volatile memory cell with the next programming duration; and   repeating the steps of determining a next programming duration and programming the non-volatile memory cell with the next programming duration until a current through the selected non-volatile memory cell during a read or verify operation is less than or equal to a first threshold current value.   
     
     
         29 . The method of  claim 26 , further comprising:
 performing a second programming process until a current through the selected non-volatile memory cell during a read or verify operation is less than or equal to a second threshold current value.   
     
     
         30 . The method of  claim 26 , wherein the performing a first programming process further comprises:
 when a current through the selected non-volatile memory cell is less than or equal to a third threshold current value, erasing the selected non-volatile memory cell and repeating the first programming process.   
     
     
         31 . The method of  claim 29 , further comprising:
 performing a third programming process until a current through the selected non-volatile memory cell during a read or verify operation is less than or equal to a fourth threshold current value.   
     
     
         32 . A method of programming a logical multi-bit cell comprising i physical non-volatile memory cells each capable of storing one of n possible values, where i is an integer greater than 1 and n is an integer greater than 1, the method comprising:
 performing a programming operation on j of the i physical non-volatile memory cells, where j is less than or equal to i until a coarse current target for the logical multi-bit cell is achieved; and   performing a programming operation on k of the j physical non-volatile memory cells, where k is less than or equal to j until a precision current target for the logical multi-bit cell is achieved.   
     
     
         33 . The method of  claim 32 , wherein the i physical non-volatile memory cells have a uniform width. 
     
     
         34 . The method of  claim 32 , wherein the i physical non-volatile memory cells have a non-uniform-width. 
     
     
         35 . A method of programming a logical multi-bit cell comprising i physical non-volatile memory cells of non-uniform width, each of the i cells capable of storing one of n possible values, where i is an integer greater than 1 and n is an integer greater than 1, the method comprising:
 performing a programming operation on j of the i physical non-volatile memory cells containing the largest width, where j is less than or equal to i until a coarse current target for the logical multi-bit cell is achieved; and   performing a programming operation on k of the j physical non-volatile memory cells containing the smallest width, where k is less than or equal to j until a precision current target for the logical multi-bit cell is achieved.