Resistive random access memory device and method for manufacturing the same

Abstract

A memory device, containing a first interconnection extending in a first direction; a first layer including tungsten nitride provided on the first interconnection; a stacked body layer provided on the first layer, a second layer including tungsten provided on the stacked body layer, a memory cell including a germanium tellurium antimony provided on the second layer, a second interconnection provided above the memory cell and extending in a second direction intersecting the first direction; and a third layer including tungsten disposed between the memory cell and the second interconnection, wherein the stacked body layer contains a first material layer of a first material which is different from a material of the first layer, and a second material layer including a second material which is different from the first material and the material of the first layer, wherein the second layer covers a lower surface of the memory cell, and wherein the third layer covers an upper surface of the memory cell.

What is claimed is: 
     
         1 . A memory device, comprising:
 a first interconnection extending in a first direction;   a first layer including tungsten nitride, the first layer being provided on the first interconnection;   a stacked body layer provided on the first layer, the stacked body layer comprising
 a first material layer including a first material, the first material layer being different from a material of the first layer, and 
 a second material layer including a second material which is different from the first material and the material of the first layer; 
   a second layer provided on the stacked body layer, the second layer including tungsten;   a memory cell provided on the second layer and including a germanium tellurium antimony;   a second interconnection provided above the memory cell and extending in a second direction intersecting the first direction; and   a third layer including tungsten disposed between the memory cell and the second interconnection, wherein   the second layer covers a lower surface of the memory cell, and   the third layer covers an upper surface of the memory cell.   
     
     
         2 . The device according to  claim 1 , wherein
 a length of the first interconnection in the first direction is longer than a length of the memory cell in the first direction, and   a length of the second interconnection in the second direction is longer than a length of the memory cell in the second direction.   
     
     
         3 . The device according to  claim 1 , wherein the first layer is provided directly on the stacked body layer. 
     
     
         4 . The device according to  claim 1 , wherein the memory cell is a resistance change layer. 
     
     
         5 . The device according to  claim 1 , wherein the stacked body layer has a resistivity higher than a resistivity of the first interconnection. 
     
     
         6 . The device according to  claim 1 , wherein the first material includes a metal element. 
     
     
         7 . The device according to  claim 1 , wherein the first material includes nitrogen. 
     
     
         8 . The device according to  claim 1 , wherein
 the first material includes one or more selected from the group consisting of silicon, titanium, tantalum, zirconium, aluminum, hafnium, molybdenum, tungsten, and vanadium, and   the second material includes a nitride or an oxide of one or more selected from the group consisting of silicon, titanium, tantalum, zirconium, aluminum, hafnium, molybdenum, tungsten, and vanadium.   
     
     
         9 . The device according to  claim 1 , wherein the first material includes silicon. 
     
     
         10 . The device according to  claim 1 , wherein
 the first material includes aluminum, and   the second material includes an aluminum nitride.