Systems and methods for executing a programmable finite state machine that accelerates fetchless computations and operations of an array of processing cores of an integrated circuit

Abstract

Systems and methods for fetchless acceleration of convolutional loops on an integrated circuit include identifying, by a compiler, finite state machine (FSM) initialization parameters based on computational requirements of a computational loop; initializing a programmable FSM based on the FSM initialization parameters, wherein the FSM initialization parameters include a loop iteration parameter identifying a number of computation cycles of the computational loop; executing the programmable FSM to enable fetchless computations by: generating a plurality of computational loop control signals including a distinct computation loop control signal for each of the number of computation cycles of the computational loop based on the loop iteration parameter; and controlling an execution of a plurality of computation cycles of a computational circuit performing the computational loop based on transmitting the plurality of computational loop control signals until the number of computation cycles of the computation loop are completed.

What is claimed: 
     
         1 . A method for accelerating an execution of computational loops on an integrated circuit, the method comprising:
 programming a finite state machine (FSM) based on a loop iteration parameter comprising a number of computation cycles of a computational loop to be executed by a computational circuit;   at runtime, executing the FSM based on a start signal, wherein executing the FSM includes:
 (i) generating, by the FSM, a plurality of control signals including a distinct control signal for each of the number of computation cycles of the computational loop; and 
 (ii) controlling, by the FSM, an operation of the computational circuit executing the computational loop based on a transmission of the plurality of control signals to the computational circuit. 
   
     
     
         2 . The method according to  claim 1 , wherein
 the FSM is controllably connected to a plurality of processing cores, each of the plurality of processing cores having at least one computational circuit.   
     
     
         3 . The method according to  claim 1 , wherein
 at runtime, the FSM is executed without performing fetches of computational loop instructions.   
     
     
         4 . The method according to  claim 1 , further comprising:
 programming the FSM based on a data movement parameter comprising at least one data movement instruction that, when executed, moves input data from a register file of a first processing core to data input ports of neighboring processing cores.   
     
     
         5 . The method according to  claim 4 , wherein
 at runtime, the FSM is executed without performing fetches of data movement instructions.   
     
     
         6 . The method according to  claim 4 , wherein
 the register file is associated with one or more data output ports of the first processing core and data input ports of the first processing core, wherein the data input ports of the first processing core are directly connected to data output ports of the neighboring processing cores; and   executing the at least one data movement instruction causes the input data to rotate an angle from the data input ports of the first processing core to the one or more data output ports of the first processing core.   
     
     
         7 . The method according to  claim 4 , wherein
 at runtime, executing the FSM causes an execution of the computational loop based on the loop iteration parameter, and   subsequently, executing the FSM causes an execution of one or more computational loops based on the loop iteration parameter and the data movement parameter.   
     
     
         8 . The method according to  claim 4 , wherein
 at runtime, the FSM generates:
 a first set of control signals of the plurality of control signals for executing the computational loop based on the loop iteration parameter; and 
 in response to completing the computational loop based on the loop iteration parameter, a second set of control signals of the plurality of control signals for executing (a) the number of computation cycles of the computational loop and (b) the at least one data movement instruction based on the loop iteration parameter and the data movement parameter. 
   
     
     
         9 . The method according to  claim 1 , wherein
 programming the FSM includes identifying, by the FSM, a distinct data movement control signal for each of the number of computation cycles of the computational loop based on the loop iteration parameter and a data movement parameter.   
     
     
         10 . The method according to  claim 9 , wherein
 controlling the operation of the computational circuit executing the computational loop includes transmitting, by the FSM, the distinct data movement control signal for each of the number of computation cycles of the computational loop until the number of computation cycles of the computational loop are completed.   
     
     
         11 . The method according to  claim 1 , wherein
 programming the FSM includes encoding a starting memory address parameter to a start memory address register file accessible to one or more computational circuits controllable by the FSM.   
     
     
         12 . The method according to  claim 11 , wherein
 the starting memory address parameter comprises a register file pointer that points to a head of input data at a location within an n-dimensional memory stored within at least one processing core controllable by the FSM.   
     
     
         13 . The method according to  claim 1 , wherein
 programming the FSM includes encoding a convolution filter size parameter to a convolution register file of at least one processing core controllable by the FSM.   
     
     
         14 . The method according to  claim 13 , wherein
 the convolution filter size parameter comprises a value that maps to one of a plurality of distinct convolutional filter sizes for a given convolutional computation by a multiply accumulator circuit of the at least one processing core.   
     
     
         15 . The method according to  claim 1 , wherein
 programming the FSM includes encoding the loop iteration parameter to a combination of distinct iteration register files of at least one processing core controllable by the FSM.   
     
     
         16 . The method according to  claim 1 , wherein:
 at runtime, the FSM generates the plurality of controls signals causing an execution of an N-way multiply accumulate with computation weights and computation input data, wherein:   N relates to a number of distinct multiply accumulate circuits concurrently executing a distinct computational loop, and   N is greater than one.   
     
     
         17 . The method according to  claim 1 , wherein
 if a convolution filter size parameter of the FSM includes a value that maps to one of a plurality of distinct convolutional filter sizes that is greater than a 1×1 convolutional filter size, the FSM broadcasts input data pointed to by a starting memory address parameter to a collection of processing cores in neighboring proximity to the FSM.   
     
     
         18 . A method comprising:
 programming a finite state machine (FSM) based on one or more FSM initialization parameters, wherein the one or more FSM initialization parameters include a loop iteration parameter comprising a number of multiply-accumulate computation cycles of a convolutional loop;   at runtime, implementing the FSM to enable one or more computations by:
 (i) generating, by the FSM, a plurality of convolutional loop control signals based on the loop iteration parameter; and 
 (ii) controlling, by the FSM, an execution of a plurality of multiply-accumulate computation cycles of a multiply accumulator circuit (MAC) performing the convolutional loop based on transmitting the plurality of convolutional loop control signals until the number of multiply-accumulate computation cycles of the convolutional loop are completed. 
   
     
     
         19 . The method according to  claim 18 , wherein
 programming the FSM includes:
 (i) programming a starting memory address parameter at a start memory address register file accessible to the MAC; 
 (ii) programming a convolution filter size parameter at a convolution register file accessible to the MAC; and 
 (iii) programming one or more iteration parameters at one or more iteration register files accessible to the FSM. 
   
     
     
         20 . A method for implementing finite state machine (FSM)-controlled convolutional computations on an integrated circuit, the method comprising:
 configuring an FSM based on one or more FSM programming instructions, wherein the FSM controls:
 (a) computations of multiply accumulator circuits (MACs) of a plurality of distinct processing cores, and 
 (b) data movement operations of data ports of the plurality of distinct processing cores; 
   wherein configuring the FSM includes:
 (1) encoding a starting memory address value to an address register file accessible to the MACs of the plurality of distinct processing cores, 
 (2) encoding a convolutional filter size to a convolutional register file associated with the FSM, and 
 (3) encoding an iteration value to at least one iteration register file associated with the FSM, wherein the iteration value identifies a number of cycles of a convolutional loop performed by at least one of the MACs; and 
   executing a Boolean switch based on the configuring of the FSM that starts an operation of the FSM for generating control signals to the MACs for automatically executing one or more distinct convolutional loops.