US2023385107A1PendingUtilityA1

Resource availability management using real-time task manager in multi-core system

Assignee: TEXAS INSTRUMENTS INCPriority: May 30, 2018Filed: Aug 14, 2023Published: Nov 30, 2023
Est. expiryMay 30, 2038(~11.9 yrs left)· nominal 20-yr term from priority
G06F 9/4881G06F 2209/503G06F 9/52G06F 9/5038G06F 1/06G06F 9/5016G06F 9/5011G06F 13/20G06F 9/448G06F 11/1004H04L 1/0041G06F 13/28G06F 13/4068G06F 2209/5012G06F 16/9035H04L 1/0061
76
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A computing resource allocation method comprises beginning a first performance of a first task; determining, using a task manager circuit during the first performance of the first task, that a first operation from among the first plurality of operations requires a resource, wherein the resource is external to the processor; determining, using a spinlock circuit, that the resource is unavailable for use; pausing, under control of the task manager, the first performance of the first task at the processor; beginning, using the processor, a second performance of a second task, the second task comprising a second plurality of operations; receiving, at the task manager, a notice from the spinlock that the resource is currently available for use by the processor; and resuming, under control of the task manager, the first performance of the first task at the processor starting with the first operation from among the first plurality of operations.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A method comprising:
 beginning, using a processor, a first processor task that uses a first shared resource;   determining, using a synchronization circuit, during the first processor task, whether the first shared resource is currently available;   based on the first shared resource being unavailable, pausing the first processor task;   receiving, from the synchronization circuit, a notice from the synchronization circuit that a resource is currently available, wherein the synchronization circuit is configured to determine and communicate availability of a plurality of shared resources that includes the first shared resource;   determining, based on the notice, that the resource that is currently available is the first shared resource; and   in response to the notice, resuming the first processor task.   
     
     
         2 . The method of  claim 1 , wherein:
 the first processor task includes a first operation;   the pausing of the first processor task occurs at the first operation; and   the resuming of the first processor task occurs at the first operation.   
     
     
         3 . The method of  claim 2 , wherein the resuming of the first processor task include changing a program counter of the processor to an address associated with the first operation. 
     
     
         4 . The method of  claim 2 , wherein the first operation uses the first shared resource. 
     
     
         5 . The method of  claim 1  further comprising after the pausing of the first processor task, beginning, using the processor, a second processor task, wherein the resuming of the first processor task includes determining whether to preempt the second processor task based on a priority of the first processor task. 
     
     
         6 . The method of  claim 5 , wherein the resuming of the first processor task includes context switching from a context associated with the second processor task to a context associated with the first processor task. 
     
     
         7 . The method of  claim 1 , wherein:
 the processor is a first processor; and   the determining of whether the first shared resource is currently available includes determining, using the synchronization circuit, whether the first shared resource is currently being used by a second processor.   
     
     
         8 . The method of  claim 1 , wherein the synchronization circuit is a spinlock circuit. 
     
     
         9 . A device comprising:
 a processor;   a task manager circuit coupled to the processor; and   a synchronization circuit coupled to the task manager circuit, wherein:
 the processor is configured to begin a first processor task that uses a first shared resource; 
 the synchronization circuit is configured to determine and communicate availability of a plurality of shared resources that includes the first shared resource; and 
 the task manager circuit is configured to:
 determine, using the synchronization circuit, whether the first shared resource is unavailable; 
 based on the first shared resource being unavailable, cause the processor to pause the first processor task; 
 receive, from the synchronization circuit, a notice from the synchronization circuit that a resource is currently available; 
 determine, based on the notice, that the resource that is currently available is the first shared resource; and 
 in response to the notice, cause the processor to resume the first processor task. 
 
   
     
     
         10 . The device of  claim 9 , wherein:
 the first processor task includes a first operation;   the pausing of the first processor task occurs at the first operation; and   the resuming of the first processor task occurs at the first operation.   
     
     
         11 . The device of  claim 10 , wherein the resuming of the first processor task include changing a program counter of the processor to an address associated with the first operation. 
     
     
         12 . The device of  claim 10 , wherein the first operation uses the first shared resource. 
     
     
         13 . The device of  claim 9 , wherein:
 the task manager circuit is configured to, after the pausing of the first processor task, cause the processor to begin a second processor task; and   the resuming of the first processor task includes determining whether to preempt the second processor task based on a priority of the first processor task.   
     
     
         14 . The device of  claim 13 , wherein the resuming of the first processor task includes context switching from a context associated with the second processor task to a context associated with the first processor task. 
     
     
         15 . The device of  claim 9 , wherein:
 the processor is a first processor;   the device further comprises a second processor; and   the synchronization circuit is configured to determine whether the first shared resource is currently available based on whether the first shared resource is currently being used by the second processor.   
     
     
         16 . The device of  claim 9 , wherein the synchronization circuit is a spinlock circuit. 
     
     
         17 . A device comprising:
 a set of processor cores that each include a respective task manager circuit;   a set of shared resources coupled to the set of processor cores; and   a synchronization circuit coupled to the set of processor cores and the set of shared resources, wherein:
 each processor core of the set of processor cores is configured to begin a respective processor task that uses a first shared resource of the set of shared resources; 
 the synchronization circuit is configured to determine and communicate availability of the set of shared resources; and 
 each task manager circuit of the set of task manager circuits is configured to:
 determine, using the synchronization circuit, whether the first shared resource is unavailable; 
 based on the first shared resource being unavailable, cause a respective processor core of the set of processor cores pause the respective processor task; 
 receive, from the synchronization circuit, a notice from the synchronization circuit that a resource is currently available; 
 determine, based on the notice, that the resource that is currently available is the first shared resource; and 
 in response to the notice, cause the respective processor core to resume the respective processor task. 
 
   
     
     
         18 . The device of  claim 17 , wherein:
 the respective processor task includes a first operation;   the pausing of the respective processor task occurs at the first operation; and   the resuming of the respective processor task occurs at the first operation.   
     
     
         19 . The device of  claim 18 , wherein the resuming of the respective processor task include changing a program counter of the respective processor core to an address associated with the first operation. 
     
     
         20 . The device of  claim 18 , wherein the first operation uses the first shared resource.

Join the waitlist — get patent alerts

Track US2023385107A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.