Low-Pincount High-Bandwidth Memory And Memory Bus

Abstract

A memory subsystem is provided, including a memory controller integrated circuit (IC), a memory bus and a memory IC, all which use fewer signals than common DDR type memory of the same peak bandwidth. Using no more than 22 switching signals, the subsystem can transfer data over 3000 Megabytes/second across the bus interconnecting the ICs. Signal count reduction is attained by time-multiplexing address/control commands onto at least some of the same signals used for data transfer. A single bus signal is used to initiate bus operation, and once in operation the single signal can transfer addressing and control information to the memory IC concurrent with data transfer via a serial protocol based on 16 bit samples of this single bus signal. Bus bandwidth can be scaled by adding additional data and data strobe IO signals. These additional data bus signals might be used only for data and data mask transport. The physical layout of one version of the memory IC dispatches switching signal terminals adjacent to one short edge of the memory die to minimize the die area overhead for controller IC memory interface circuitry when used in a stacked die multi-chip package with said memory controller IC. The memory IC interface signal placement and signal count minimize signal length and circuitry for the memory bus signals.

1 . A data processing system, comprising:
 at least one memory device containing mode register programmable bus termination circuits, wherein the bus termination circuits comprise series resistor termination and parallel resistor termination circuits contained within the memory device; and   a bus connecting the at least one memory device to a memory controller, the bus comprising data bus, data strobe, address, and command signal wire elements;   wherein the mode register programmable bus termination circuits can be selectively connected, under mode register control, to each of the data bus, data strobe, address and command signal wire elements.   
     
     
         2 . The data processing system of  claim 1 , wherein a non-bus connectable node of each of the parallel resistor termination circuits is connectable to a non-ground node. 
     
     
         3 . The data processing system of  claim 1 , wherein the at least one memory device comprises a Dynamic Random Access Memory (“DRAM”). 
     
     
         4 . The data processing system of  claim 3 , wherein said DRAM is contained in a fan-in wafer level chip scale package. 
     
     
         5 . The data processing system of  claim 4 , wherein two DRAMs are connected to the memory controller using a common bus. 
     
     
         6 . The data processing system of  claim 1 , wherein the address and command signals are carried by the same physical conductors in said memory bus. 
     
     
         7 . The data processing system of  claim 1 , wherein mode register contents can be dynamically reconfigured. 
     
     
         8 . The data processing system of  claim 1 , wherein the series termination circuit comprises a resister in series with an output driver. 
     
     
         9 . The data processing system of  claim 1 , wherein the series termination circuit sets an output impedance. 
     
     
         10 . A memory device that has external terminals configured for coupling to a memory bus, said memory device containing mode register programmable bus termination circuits that can be selectively connected, under mode register control, to each of a data bus, data strobe, address and command signal wire elements comprising said memory bus wherein bus termination circuits comprise series resistor termination and parallel resistor termination circuits contained within the memory device. 
     
     
         11 . The memory device of  claim 10 , wherein a non-bus connectable node of each of the parallel resistor termination circuits is connectable to a non-ground node. 
     
     
         12 . The memory device of  claim 10 , wherein the memory device comprises a Dynamic Random Access Memory (“DRAM”). 
     
     
         13 . The memory device of  claim 12 , wherein the DRAM is contained within a fan-in wafer level chip scale package. 
     
     
         14 . The memory device of  claim 10 , wherein mode register contents can be dynamically reconfigured. 
     
     
         15 . The memory device of  claim 10 , wherein the series resistor termination circuit comprises a resister in series with an output driver. 
     
     
         16 . The memory device of  claim 10 , wherein the series resistor termination circuit sets an output impedance. 
     
     
         17 . A method for dynamically minimizing memory bus power in a data processing system that contains at least one Dynamic Random Access Memory (“DRAM”) and memory bus therefor, said method comprising dynamically changing an operating frequency and bus termination scheme for said memory bus, wherein at high operating frequency, parallel bus termination is used and at reduced operating frequency, series termination is used to reduce termination power and wherein the parallel bus termination is not limited to ground referencing.