Secure tamper resistant smart card

Abstract

Systems, devices, and methods for secure data management and transfer for secure data transactions are provided. For example, disclosed herein are secure & tamper resistant smart cards configured to immutably store data and securely exchange at least a portion of the data via, for example, wireless networks and/or peer-to-peer networks. The smart cards comprise a plurality of dedicated hardware circuit blocks electrically coupled via a bus interconnection, the plurality of dedicated hardware circuit blocks configured to authenticate users, verify trust amongst the smart card and external devices, and encrypt sensitive data for secure transmission.

What is claimed is: 
     
         1 . A smart card comprising:
 a plurality of dedicated hardware circuit blocks electrically coupled via a bus interconnection, the plurality of dedicated hardware circuit blocks comprising:
 an identification input circuity configured to capture user credentials from an interaction by a user with the smart card; 
 memory circuitry configured to store an identification template corresponding to one or more registered users of the smart card; 
 user identification circuitry coupled to the memory and electrically coupled to the identification input circuity, the identification circuitry configured to authenticate that user credentials received from the identification input circuity correspond to the one or more registered users; and 
 a microcontroller comprising one or more processors and configured to schedule set up and execution of the dedicated hardware blocks; 
 wherein the user credentials comprise an image and wherein the user identification circuitry comprises (i) an image enhancement block configured to perform image processing on the image, (ii) a minutiae detection block configured to detect minutiae of the image, and (iii) a comparison block configured to compare the image against the identification template retrieved from the memory circuit; 
 wherein each of the image enhancement block, minutiae detection block, and comparison block is one of the plurality of dedicated hardware circuit blocks, and configured for reduced data bit widths based on sequential and parallel processing.