Monolithic multi-fets

Abstract

A monolithic multi-FET transistor comprises an epitaxial layer disposed on a dielectric layer. The epitaxial layer comprises a crystalline semiconductor material and a multi-FET area. An isolation structure surrounds the multi-FET area and divides the multi-FET area into separate FET portions. A gate disposed on a gate dielectric extends over each FET portion. A source and a drain are each disposed on opposite sides of the gate on the epitaxial layer within each FET portion. Each gate, source, and drain comprise a separate electrical conductor and the gate, source, drain, and epitaxial layer within each FET portion form a field-effect transistor. Gate, source, and drain contacts electrically connect the gates, sources, and drains of the separate FET portions, respectively. At least the sources or drains of two neighboring FET portions are disposed in common over at least a portion of the isolation structure dividing the two neighboring FET portions.

What is claimed: 
     
         1 . A monolithic multi-FET transistor, comprising:
 a semiconductor substrate comprising a bulk layer, a dielectric layer disposed on the bulk layer, and an epitaxial layer disposed on the dielectric layer, the bulk layer and the epitaxial layer both comprising a crystalline semiconductor material, and the epitaxial layer comprising a multi-FET area;   an isolation structure disposed in the epitaxial layer and extending from the dielectric layer through the epitaxial layer to a surface of the epitaxial layer opposite the dielectric layer, the isolation structure surrounding the multi-FET area and dividing the multi-FET area into separate FET portions;   for each separate FET portion of the separate FET portions:
 a respective gate dielectric that extends over the separate FET portion that contacts the isolation structure at two separated locations; 
 a respective gate disposed on the respective gate dielectric; 
 a respective source disposed on the epitaxial layer on a side of the respective gate; and 
 a respective drain disposed on the epitaxial layer on a side of the respective gate opposite the respective source, 
 wherein at least the respective gate, the respective source, the respective drain and the separate FET portion of the epitaxial layer form a field-effect transistor (FET); and 
   a gate contact electrically connecting the respective gate of each of the separate FET portions, a source contact electrically connecting the respective source of each of the separate FET portions, and a drain contact electrically connecting the respective drain of each of the FET portions,   wherein at least one of (i) the respective source for two neighboring FET portions of the separate FET portions is a common source disposed over at least a portion of the isolation structure dividing the two neighboring FET portions and (ii) the respective drain for two neighboring FET portions is a common drain disposed over at least a portion of the isolation structure dividing the two neighboring FET portions.   
     
     
         2 . The monolithic multi-FET transistor of  claim 1 , wherein the separate FET portions comprise three or more separate FET portions and at least the respective source for two first neighboring FET portions is a common source disposed over the isolation structure separating the two first neighboring FET portions and the respective drains for two second neighboring FET portions is a common drain disposed over the isolation structure separating the two second neighboring FET portions (e.g., and one of the two first neighboring FET portions is one of the two second neighboring FET portions). 
     
     
         3 . The monolithic multi-FET transistor of  claim 1 , wherein the isolation structure divides the multi-FET area into a one-dimensional array of separate FET portions. 
     
     
         4 . The monolithic multi-FET transistor of  claim 1 , wherein the isolation structure divides the multi-FET area into a two-dimensional array of separate FET portions. 
     
     
         5 . The monolithic multi-FET transistor of  claim 4 , wherein the two neighboring FET portions are first neighboring FET portions adjacent in a first dimension of the two-dimensional array and two other neighboring FET portions in a second dimension of the two-dimensional array are second neighboring FET portions and the respective gate of the second neighboring FET portions is a common gate disposed over the isolation structure dividing the two second neighboring FET portions, the respective source of the second neighboring FET portions is a common source disposed over the isolation structure dividing the two second neighboring FET portions, and the respective drain of the second neighboring FET portions are a common drain disposed over the isolation structure dividing the two second neighboring FET portions. 
     
     
         6 . The monolithic multi-FET transistor of  claim 1 , wherein the semiconductor substrate comprises silicon. 
     
     
         7 . The monolithic multi-FET transistor of  claim 1 , wherein the semiconductor substrate comprises a compound semiconductor. 
     
     
         8 . The monolithic multi-FET transistor of  claim 1 , wherein the epitaxial layer and the bulk layer comprise a common material. 
     
     
         9 . The monolithic multi-FET transistor of  claim 1 , wherein the epitaxial layer and the bulk layer comprise different materials. 
     
     
         10 . The monolithic multi-FET transistor of  claim 1 , wherein the semiconductor substrate is a silicon-on-insulator substrate. 
     
     
         11 . The monolithic multi-FET transistor of  claim 1 , wherein the dielectric layer is a buried oxide layer. 
     
     
         12 . The monolithic multi-FET transistor of  claim 1 , wherein the respective gate dielectric is a gate oxide. 
     
     
         13 . The monolithic multi-FET transistor of  claim 1 , wherein the monolithic multi-FET transistor is a power transistor. 
     
     
         14 . The monolithic multi-FET transistor of  claim 1 , wherein (i) the respective gate is linear, (ii) the respective source is linear, (iii) the respective drain is linear, or (iv) any combination of (i), (ii), and (iii). 
     
     
         15 . The monolithic multi-FET transistor of  claim 1 , wherein (i) the respective gate has a gate end and the gate contact connects to the respective gate at the gate end, (ii) the respective source has a source end and the source contact connects to the respective source at the source end, (iii) the respective drain has a drain end and the drain contact connects to the respective drain at the drain end, or (iv) any combination of (i), (ii), and (iii). 
     
     
         16 . The monolithic multi-FET transistor of  claim 1 , wherein (i) the respective gate has two opposing gate ends and the gate ends are both electrically connected with the gate contact, (ii) the respective source has two opposing source ends and the source ends are both electrically connected with the source contact, (iii) the respective drain has two opposing drain ends and the drain ends are both electrically connected with the drain contact, or (iv) any combination of (i), (ii), and (iii). 
     
     
         17 . The monolithic multi-FET transistor of  claim 1 , wherein (i) the gate contact is disposed at least partially over the respective gate, (ii) the source contact is disposed at least partially over the respective source, (iii) the drain contact is disposed at least partially over the respective drain, or (iv) any combination of (i), (ii), and (iii). 
     
     
         18 . The monolithic multi-FET transistor of  claim 1 , wherein R C <(R E −R T ), where R C  is the sum of the resistances of contact portions of the gate contact, source contact, or drain contact, R T  is the resistance of the respective gate, the respective source, or the respective drain, respectively, and R E  is the resistance of an equivalent gate, an equivalent source, or an equivalent drain, respectively. 
     
     
         19 . The monolithic multi-FET transistor of  claim 1 , wherein (i) the gate contact is more electrically conductive than the respective gate, (ii) the source contact is more electrically conductive than the respective source, (iii) the drain contact is more electrically conductive than the respective drain, or (iv) any combination of (i), (ii), and (iii). 
     
     
         20 . A monolithic multi-FET wafer, comprising a plurality of monolithic multi-FET transistors of  claim 1 , wherein the semiconductor substrate is common to the plurality of monolithic multi-FET transistors. 
     
     
         21 . The monolithic multi-FET wafer of  claim 20 , wherein the bulk layer comprises a sacrificial layer comprising separate sacrificial portions and anchor portions and each of the plurality of monolithic multi-FET transistors is entirely disposed over a sacrificial portion and is physically connected to an anchor portion of the anchor portions with at least one tether. 
     
     
         22 . A monolithic multi-FET system, comprising:
 a monolithic multi-FET transistor according to  claim 1 ;   a multi-FET controller disposed on or over the monolithic multi-FET transistor; and   electrical conductors electrically connecting the multi-FET controller to the monolithic multi-FET transistor, the multi-FET controller operable to control the multi-FET transistor.   
     
     
         23 . The monolithic multi-FET system of  claim 22 , wherein the multi-FET controller comprises a broken or separated tether. 
     
     
         24 . The monolithic multi-FET system of  claim 22 , comprising a layer of adhesive adhering the multi-FET controller to the monolithic multi-FET transistor. 
     
     
         25 . The monolithic multi-FET system of  claim 22 , wherein the multi-FET controller comprises a semiconductor material that is different from the crystalline semiconductor material of the epitaxial layer. 
     
     
         26 . A monolithic multi-FET system, comprising:
 a first monolithic multi-FET transistor according to  claims 1 ; and   a second monolithic multi-FET transistor according to  claim 1 ,   wherein the second monolithic multi-FET transistor is disposed on or over the first monolithic multi-FET transistor and   an electrical conductor electrically connects the gate contact of the first monolithic multi-FET transistor to the gate contact of the second monolithic multi-FET transistor,   an electrical conductor electrically connects the source contact of the first monolithic multi-FET transistor to the source contact of the second monolithic multi-FET transistor, and   an electrical conductor electrically connects the drain contact of the first monolithic multi-FET transistor to the drain contact of the second monolithic multi-FET transistor,   so that the first monolithic multi-FET transistor and the second monolithic multi-FET transistor are electrically connected in parallel.   
     
     
         27 . The monolithic multi-FET system of  claim 26 , wherein the first monolithic multi-FET transistor has a first area and the second monolithic multi-FET transistor has a second area, and the first area is greater than the second area. 
     
     
         28 . The monolithic multi-FET system of  claim 26 , wherein the first monolithic multi-FET transistor has a first number of FETs and the second monolithic multi-FET transistor has a second number of FETs, and the first number of FETs is greater than the second number of FETs. 
     
     
         29 . A method of making a monolithic multi-FET wafer, comprising:
 providing a semiconductor substrate comprising a bulk layer, a dielectric layer disposed on the bulk layer, and an epitaxial layer disposed on the dielectric layer, the bulk layer and the epitaxial layer both comprising a crystalline semiconductor material, and the epitaxial layer comprising a multi-FET area;   disposing an isolation structure in the epitaxial layer and extending from a surface of the epitaxial layer through the epitaxial layer to the dielectric layer, the isolation structure surrounding the multi-FET area and dividing the multi-FET area into separate FET portions; and   forming a plurality of monolithic multi-FETs on the semiconductor substrate, the forming comprising:
 disposing gate dielectrics that each extend over a different FET portion of the separate FET portions and contacts the isolation structure at two separated locations; 
 disposing a gate on each gate dielectric of the gate dielectrics, a source on the epitaxial layer within each FET portion of the separate FET portions on a side of the gate, and a drain on the epitaxial layer within each FET portion of the separate FET portions on a side of the gate opposite the source, wherein each gate, source, and drain comprise a separate electrical conductor; and 
 electrically connecting (i) the gate of each of the separate FET portions with a gate contact, (ii) the source of each of the separate FET portions with a source contact, (iii) and the drain of each of the separate FET portions with a drain contact, 
 wherein at least one of (i) the source of each of two neighboring FET portions of the separate FET portions is a common source disposed over at least a portion of the isolation structure dividing the two neighboring FET portions and (ii) the drain of each of two neighboring FET portions is a common drain disposed over at least a portion of the isolation structure dividing the two neighboring FET portions. 
   
     
     
         30 . The method of  claim 29 , wherein providing the semiconductor substrate includes providing the bulk layer comprising a sacrificial layer comprising separate sacrificial portions and anchor portions and wherein each of the plurality of multi-FET transistors is entirely disposed over one of the sacrificial portions and is physically connected to an anchor portion of the anchor portions with at least one tether. 
     
     
         31 . The method of  claim 30 , comprising providing a target substrate, etching the sacrificial portions, and printing the plurality of monolithic multi-FET transistors from the bulk layer to the target substrate. 
     
     
         32 . A method of making a monolithic multi-FET system, comprising:
 providing a monolithic multi-FET transistor according to  claim 1 ;   providing a multi-FET controller; and   disposing the multi-FET controller over or on the monolithic multi-FET transistor;   electrically connecting the multi-FET controller to the monolithic multi-FET transistor with electrical conductors, the multi-FET controller operable to control the multi-FET transistor.   
     
     
         33 . The method of  claim 32 , wherein disposing the multi-FET controller comprises printing the multi-FET controller from a multi-FET controller source wafer to the monolithic multi-FET transistor. 
     
     
         34 . A method of making a monolithic multi-FET system, comprising:
 providing a first monolithic multi-FET transistor according to  claim 1 ;   providing a second monolithic multi-FET transistor according to  claim 1 ;   disposing the second monolithic multi-FET transistor on or over the first monolithic multi-FET transistor;   electrically connecting the gate contact of the first monolithic multi-FET transistor to the gate contact of the second monolithic multi-FET transistor;   electrically connecting the source contact of the first monolithic multi-FET transistor to the source contact of the second monolithic multi-FET transistor; and   electrically connecting the drain contact of the first monolithic multi-FET transistor to the drain contact of the second monolithic multi-FET transistor,   so that the first monolithic multi-FET transistor and the second monolithic multi-FET transistor are electrically connected in parallel.   
     
     
         35 . A monolithic multi-FET transistor, comprising:
 a dielectric layer and an epitaxial layer disposed on the dielectric layer, the epitaxial layer comprising a crystalline semiconductor material and a multi-FET area;   an isolation structure disposed in the epitaxial layer and extending from the dielectric layer through the epitaxial layer to a surface of the epitaxial layer opposite the dielectric layer, the isolation structure surrounding the multi-FET area and dividing the multi-FET area into separate FET portions;   for each separate FET portion of the separate FET portions:
 a respective gate dielectric that extends over the separate FET portion that contacts the isolation structure at two separated locations; 
 a respective gate disposed on the respective gate dielectric; 
 a respective source disposed on the epitaxial layer on a side of the respective gate; 
 a respective drain disposed on the epitaxial layer on a side of the respective gate opposite the respective source, 
 wherein at least the respective gate, the respective source, the respective drain and the separate FET portion of the epitaxial layer form a field-effect transistor (FET); 
   a gate contact electrically connecting the respective gate of each of the separate FET portions, a source contact electrically connecting the respective source of each of the separate FET portions, and a drain contact electrically connecting the respective drain of each of the FET portions,   wherein at least one of (i) the respective source for two neighboring FET portions of the separate FET portions is a common source disposed over at least a portion of the isolation structure dividing the two neighboring FET portions and (ii) the respective drain for two neighboring FET portions is a common drain disposed over at least a portion of the isolation structure dividing the two neighboring FET portions.   
     
     
         36 . The monolithic multi-FET transistor of  claim 35 , wherein the separate FET portions comprise three or more separate FET portions and at least the respective source for two first neighboring FET portions is a common source disposed over the isolation structure separating the two first neighboring FET portions and the respective drains of for two second neighboring FET portions is a common drain disposed over the isolation structure separating the two second neighboring FET portions (e.g., and one of the two first neighboring FET portions is one of the two second neighboring FET portions). 
     
     
         37 . The monolithic multi-FET transistor of  claim 35 , wherein the isolation structure divides the multi-FET area into a one-dimensional array of separate FET portions. 
     
     
         38 . The monolithic multi-FET transistor of  claim 35 , wherein the isolation structure divides the multi-FET area into a two-dimensional array of separate FET portions. 
     
     
         39 . The monolithic multi-FET transistor of  claim 38 , wherein the two neighboring FET portions are first neighboring FET portions adjacent in a first dimension of the two-dimensional array and two other neighboring FET portions in a second dimension of the two-dimensional array are second neighboring FET portions and the respective gate of the second neighboring FET portions is a common gate disposed over the isolation structure dividing the two second neighboring FET portions, the respective source of the second neighboring FET portions is a common source disposed over the isolation structure dividing the two second neighboring FET portions, and the respective drain of the second neighboring FET portions are a common drain disposed over the isolation structure dividing the two second neighboring FET portions. 
     
     
         40 . The monolithic multi-FET transistor of  claim 35 , wherein the epitaxial layer comprises silicon. 
     
     
         41 . The monolithic multi-FET transistor of  claim 35 , wherein the epitaxial layer comprises a compound semiconductor. 
     
     
         42 . The monolithic multi-FET transistor of  claim 35 , wherein the dielectric layer is a buried oxide layer. 
     
     
         43 . The monolithic multi-FET transistor of  claim 35 , wherein the respective gate dielectric is a gate oxide. 
     
     
         44 . The monolithic multi-FET transistor of  claim 35 , wherein the monolithic multi-FET transistor is a power transistor. 
     
     
         45 . The monolithic multi-FET transistor of  claim 35 , wherein (i) the respective gate is linear, (ii) the respective source is linear, (iii) the respective drain is linear, or (iv) any combination of (i), (ii), and (iii). 
     
     
         46 . The monolithic multi-FET transistor of  claim 35 , wherein (i) the respective gate has a gate end and the gate contact connects to the respective gate at the gate end, (ii) the respective source has a source end and the source contact connects to the respective source at the source end, (iii) the respective drain has a drain end and the drain contact connects to the respective drain at the drain end, or (iv) any combination of (i), (ii), and (iii). 
     
     
         47 . The monolithic multi-FET transistor of  claim 35 , wherein (i) the respective gate has two opposing gate ends and the gate ends are both electrically connected with the gate contact, (ii) the respective source has two opposing source ends and the source ends are both electrically connected with the source contact, (iii) the respective drain has two opposing drain ends and the drain ends are both electrically connected with the drain contact, or (iv) any combination of (i), (ii), and (iii). 
     
     
         48 . The monolithic multi-FET transistor of  claim 35 , wherein (i) the gate contact is disposed at least partially over the respective gate, (ii) the source contact is disposed at least partially over the respective source, (iii) the drain contact is disposed at least partially over the respective drain, or (iv) any combination of (i), (ii), and (iii). 
     
     
         49 . The monolithic multi-FET transistor of  claim 35 , wherein R C <(R E −R T ), where R C  is the sum of the resistances of contact portions of the gate contact, source contact, or drain contact, R T  is the resistance of the respective gate, the respective source, or the respective drain, respectively, and R E  is the resistance of an equivalent gate, an equivalent source, or an equivalent drain, respectively. 
     
     
         50 . The monolithic multi-FET transistor of  claim 35 , wherein (i) the gate contact is more electrically conductive than the respective gate, (ii) the source contact is more electrically conductive than the respective source, (iii) the drain contact is more electrically conductive than the respective drain, or (iv) any combination of (i), (ii), and (iii). 
     
     
         51 . A monolithic multi-FET wafer, comprising a bulk layer of semiconductor material and a plurality of monolithic multi-FET transistors of  claim 35 , the dielectric layer of each monolithic multi-FET transistors of the plurality of multi-FET transistors disposed on the bulk layer wherein the bulk layer is common to the plurality of monolithic multi-FET transistors. 
     
     
         52 . The monolithic multi-FET wafer of  claim 51  wherein the bulk layer comprises a sacrificial layer comprising separate sacrificial portions and anchor portions and each of the plurality of monolithic multi-FET transistors is entirely disposed over one of the sacrificial portions and is physically connected to an anchor portion of the anchor portions with at least one tether. 
     
     
         53 . A monolithic multi-FET system, comprising:
 a monolithic multi-FET transistor according to  claim 35 ;   a multi-FET controller disposed on or over the monolithic multi-FET transistor; and   electrical conductors electrically connecting the multi-FET controller to the monolithic multi-FET transistor, the multi-FET controller operable to control the multi-FET transistor.   
     
     
         54 . The monolithic multi-FET system of  claim 53 , wherein the multi-FET controller comprises a broken or separated tether. 
     
     
         55 . The monolithic multi-FET system of  claim 53 , comprising a layer of adhesive adhering the multi-FET controller to the monolithic multi-FET transistor. 
     
     
         56 . The monolithic multi-FET system of  claim 53 , wherein the multi-FET controller comprises a semiconductor material that is different from the crystalline semiconductor material of the epitaxial layer. 
     
     
         57 . A monolithic multi-FET system, comprising:
 a first monolithic multi-FET transistor according to  claim 35 ; and   a second monolithic multi-FET transistor according to  claim 35 ,   wherein the second monolithic multi-FET transistor is disposed on or over the first monolithic multi-FET transistor and   an electrical conductor electrically connects the gate contact of the first monolithic multi-FET transistor to the gate contact of the second monolithic multi-FET transistor,   an electrical conductor electrically connects the source contact of the first monolithic multi-FET transistor to the source contact of the second monolithic multi-FET transistor, and   an electrical conductor electrically connects the drain contact of the first monolithic multi-FET transistor to the drain contact of the second monolithic multi-FET transistor,   so that the first monolithic multi-FET transistor and the second monolithic multi-FET transistor are electrically connected in parallel.   
     
     
         58 . The monolithic multi-FET system of  claim 57 , wherein the first monolithic multi-FET transistor has a first area and the second monolithic multi-FET transistor has a second area, and the first area is greater than the second area. 
     
     
         59 . The monolithic multi-FET system of  claim 57 , wherein the first monolithic multi-FET transistor has a first number of FETs and the second monolithic multi-FET transistor has a second number of FETs, and the first number of FETs is greater than the second number of FETs. 
     
     
         60 . A method of making a monolithic multi-FET wafer, comprising:
 providing a dielectric layer and an epitaxial layer disposed on the dielectric layer, the epitaxial layer comprising a crystalline semiconductor material and a multi-FET area;   disposing an isolation structure in the epitaxial layer and extending from a surface of the epitaxial layer through the epitaxial layer to the dielectric layer, the isolation structure surrounding the multi-FET area and dividing the multi-FET area into separate FET portions; and   forming a plurality of monolithic multi-FETs on the semiconductor substrate, the forming comprising:
 disposing gate dielectrics that each extend over a different FET portion of the separate FET portions and contacts the isolation structure at two separated locations; 
 disposing a gate on each gate dielectric of the gate dielectrics, a source on the epitaxial layer within each FET portion of the separate FET portions on a side of the gate, and a drain on the epitaxial layer within each FET portion of the separate FET portions on a side of the gate opposite the source, wherein each gate, source, and drain comprise a separate electrical conductor; and 
 electrically connecting (i) the gate of each of the separate FET portions with a gate contact, (ii) the source of each of the separate FET portions with a source contact, (iii) and the drain of each of the separate FET portions with a drain contact,
 wherein at least one of (i) the source of each of two neighboring FET portions of the separate FET portions is a common source disposed over at least a portion of the isolation structure dividing the two neighboring FET portions and (ii) the drain of each of two neighboring FET portions is a common drain disposed over at least a portion of the isolation structure dividing the two neighboring FET portions. 
 
   
     
     
         61 . The method of  claim 60 , wherein providing the epitaxial layer and the dielectric layer comprises providing a semiconductor substrate comprising a bulk layer on which the dielectric layer is disposed, the bulk layer comprising a sacrificial layer comprising separate sacrificial portions and anchor portions and wherein each of the plurality of monolithic multi-FET transistors is entirely disposed over one of the separate sacrificial portions and is physically connected to an anchor portion of the anchor portions with at least one tether. 
     
     
         62 . The method of  claim 61 , comprising providing a target substrate, etching the sacrificial portions, and printing the plurality of monolithic multi-FET transistors from the bulk layer to the target substrate. 
     
     
         63 . A method of making a monolithic multi-FET system, comprising:
 providing a monolithic multi-FET transistor according to  claim 35 ;   providing a multi-FET controller;   disposing the multi-FET controller over or on the monolithic multi-FET transistor; and   electrically connecting the multi-FET controller to the monolithic multi-FET transistor with electrical conductors, the multi-FET controller operable to control the multi-FET transistor.   
     
     
         64 . The method of  claim 63 , wherein disposing the multi-FET controller comprises printing the multi-FET controller from a multi-FET controller source wafer to the monolithic multi-FET transistor. 
     
     
         65 . A method of making a monolithic multi-FET system, comprising:
 providing a first monolithic multi-FET transistor according to  claim 35 ;   providing a second monolithic multi-FET transistor according to  claim 35 ;   disposing the second monolithic multi-FET transistor on or over the first monolithic multi-FET transistor;   electrically connecting the gate contact of the first monolithic multi-FET transistor to the gate contact of the second monolithic multi-FET transistor;   electrically connecting the source contact of the first monolithic multi-FET transistor to the source contact of the second monolithic multi-FET transistor; and   electrically connecting the drain contact of the first monolithic multi-FET transistor to the drain contact of the second monolithic multi-FET transistor,   so that the first monolithic multi-FET transistor and the second monolithic multi-FET transistor are electrically connected in parallel.   
     
     
         66 . A monolithic multi-FET transistor, comprising:
 a semiconductor substrate comprising a semiconductor epitaxial layer;   an isolation structure disposed in, and extending through, the epitaxial layer, the isolation structure defining separate FET portions;   respective field-effect transistors (FETs), each disposed on one of the separate FET portions and comprising a gate, a source, and a drain,   wherein the gates of the respective FETs are electrically connected together, the sources of the respective FETs are electrically connected together, and the drains of the respective FETs are electrically connected together, and   wherein at least one of (i) two of the respective FETs comprise a common source that extends over the isolation structure and (ii) two of the respective FETs comprise a common source that extends over the isolation structure.   
     
     
         67 . A method of making a monolithic multi-FET transistor, comprising:
 providing a semiconductor substrate comprising a semiconductor epitaxial layer;   patterning an isolation structure disposed in, and extending through, the epitaxial layer, the isolation structure defining separate FET portions;   forming respective field-effect transistors (FETs), each disposed on one of the separate FET portions and comprising a gate, a source, and a drain, wherein at least one of (i) two of the respective FETs comprise a common source that extends over the isolation structure and (ii) two of the respective FETs comprise a common source that extends over the isolation structure; and   electrically connecting (i) the gate of each of the respective FETs together, (ii) the source of each of the respective FETs together, and (iii) the drain of each of the respective FETs together.   
     
     
         68 . A monolithic multi-FET transistor, comprising:
 a substrate comprising a patterned single-crystalline semiconductor epitaxial layer defining separate FET portions; and   a plurality of FETs disposed on the substrate, wherein each of the plurality of FETs comprises one of the separate FET portions.   
     
     
         69 . The monolithic multi-FET transistor of  claim 68 , wherein the separate FET portions of the epitaxial layer are isolated by a common isolation structure. 
     
     
         70 . The monolithic multi-FET transistor of  claim 69 , wherein the isolation structure is a patterned isolation structure extending through the epitaxial layer. 
     
     
         71 . The monolithic multi-FET transistor of  claim 68 , wherein at least one of (i) two of the plurality of FETs comprise a common drain, and (ii) two of the plurality of FETs comprise a common source. 
     
     
         72 . The monolithic multi-FET transistor of  claim 71 , wherein (i) the two of the plurality of FETs comprises the common drain and the common drain extends over a common isolation structure separating the separate FET portions, (ii) the two of the plurality of FETs comprises the common source and the common source extends over a common isolation structure separating the separate FET portions, or both (i) and (ii). 
     
     
         73 . The monolithic multi-FET transistor of  claim 71 , wherein each of the plurality of FETs comprises a gate, a drain, and a source and the gates are electrically connected by a gate conductor, the drains are electrically connected by a drain conductor, and the sources are electrically connected by a source conductor. 
     
     
         74 . The monolithic multi-FET transistor of  claim 68 , wherein the substrate comprises an insulating (e.g., dielectric) layer and the patterned epitaxial layer is disposed on the insulating layer. 
     
     
         75 . The monolithic multi-FET transistor of  claim 74 , wherein the substrate comprises a bulk semiconductor layer and the insulating layer is disposed on the bulk semiconductor layer. 
     
     
         76 . The monolithic multi-FET transistor of  claim 68 , wherein the substrate is a silicon-on-insulator (SOI) substrate. 
     
     
         77 . The monolithic multi-FET transistor of  claim 68 , wherein each of the plurality of FETs comprises a gate, a gate dielectric, a source, a drain and the one of the separate FET portions. 
     
     
         78 . The monolithic multi-FET transistor of  claim 77 , wherein the gate dielectric spans the one of the separate FET portions and the source is disposed on a first side of the gate dielectric and the drain is disposed on an opposing second side of the dielectric. 
     
     
         79 . The monolithic multi-FET transistor of  claim 78 , wherein ends of the gate dielectric are disposed on an isolation structure surrounding the one of the separate FET portions. 
     
     
         80 . The monolithic multi-FET transistor of  claim 68 , wherein the monolithic multi-FET transistor is one according to any one of  claims 1 - 19  and  35 - 50 . 
     
     
         81 . A monolithic multi-FET transistor system, comprising a first monolithic multi-FET transistor of  claim 68  and a second monolithic multi-FET transistor of  claim 68 , wherein each of the FETs of the first monolithic multi-FET transistor and each of the FETs of the second monolithic multi-FET transistor comprises a respective gate, a respective source, and a respective drain. 
     
     
         82 . The monolithic multi-FET transistor system of  claim 81 , wherein the substrate of the first monolithic multi-FET transistor is separate from the substrate of the second monolithic multi-FET transistor. 
     
     
         83 . The monolithic multi-FET transistor system of  claim 81 , wherein the second monolithic multi-FET transistor is non-native to the first monolithic multi-FET transistor (e.g., has been printed onto the first monolithic multi-FET transistor). 
     
     
         84 . The monolithic multi-FET transistor system of  claim 81 , wherein one or more of (i) the respective sources of two of the FETs of the first monolithic multi-FET transistor are a common source, (ii) the respective drains of two of the FETs of the first monolithic multi-FET transistor are a common drain, (iii) the respective sources of two of the FETs of the second monolithic multi-FET transistor are a common source, and (iv) the respective drains of two of the FETs of the second monolithic multi-FET transistor are a common drain. 
     
     
         85 . A monolithic multi-FET transistor system, comprising:
 a monolithic multi-FET transistor according to  claim 68 ;   a multi-FET controller disposed on the monolithic multi-FET transistor; and   one or more electrical conductors electrically connecting the multi-FET controller to the monolithic multi-FET transistor, the multi-FET controller operable to control the multi-FET transistor.   
     
     
         86 . The monolithic multi-FET transistor system of  claim 85 , wherein the multi-FET controller comprises a substrate comprising a semiconductor material that is different from a semiconductor material in the substrate of the monolithic multi-FET transistor. 
     
     
         87 . The monolithic multi-FET transistor system of  claim 86 , wherein the semiconductor material in the substrate of the monolithic multi-FET transistor is a semiconductor material of the epitaxial layer. 
     
     
         88 . The monolithic multi-FET transistor system of  claim 85 , wherein the substrate of the monolithic multi-FET transistor comprises a bulk semiconductor layer and the semiconductor material in the substrate of the monolithic multi-FET transistor is a semiconductor material of a bulk semiconductor layer. 
     
     
         89 . The monolithic multi-FET transistor system of  claim 85 , wherein the multi-FET controller is non-native to the monolithic multi-FET transistor (e.g., has been printed onto the monolithic multi-FET transistor). 
     
     
         90 . A method of making a monolithic multi-FET transistor, comprising:
 providing a substrate comprising a single-crystalline semiconductor epitaxial layer;   electrically isolating separate FET portions of the epitaxial layer; and   forming a plurality of FETs on the substrate, wherein each of the plurality of FETs comprises one of the separate FET portions of the epitaxial layer.   
     
     
         91 . The method of  claim 90 , wherein electrically isolating the separate portions comprises patterning a common isolation structure in the epitaxial layer. 
     
     
         92 . The method of  claim 90 , wherein each of the plurality of FETs comprises a respective gate, a respective drain, and a respective source and at least one of (i) the respective drains of two of the plurality of FETs are a common drain and (ii) the respective sources of two of the plurality of FETs are a common source. 
     
     
         93 . The method of  claim 90 , wherein each of the plurality of FETs comprises a respective gate, a respective drain, and a respective source and the method further comprises:
 electrically connecting the respective drain of each of the plurality of FETs together with a drain conductor;   electrically connecting the respective source of each of the plurality of FETs together with a source conductor; and   electrically connecting the respective gate of each of the plurality of FETs together with a gate conductor.   
     
     
         94 . The method of  claim 90 , wherein providing the substrate comprises providing a substrate comprising an insulating (e.g., dielectric) layer and forming the epitaxial layer on the insulating layer. 
     
     
         95 . The method of  claim 94 , wherein the substrate is a silicon-on-insulator (SOI) substrate.