Reduced cross-talk in color and infrared image sensor

Abstract

Various embodiments of the present disclosure are directed towards an image sensor device including a first image sensor element and a second image sensor element disposed within a substrate. An interconnect structure is disposed along a front-side surface of the substrate and comprises a plurality of conductive wires, a plurality of conductive vias, and a first absorption structure. The first image sensor element is configured to generate electrical signals from electromagnetic radiation within a first range of wavelengths. The second image sensor element is configured to generate electrical signals from the electromagnetic radiation within a second range of wavelengths that is different than the first range of wavelengths. The second image sensor element is laterally adjacent to the first image sensor element. Further, the first image sensor element overlies the first absorption structure and is spaced laterally between opposing sidewalls of the first absorption structure.

1 . An image sensor device, comprising:
 a substrate having a front-side surface opposite a back-side surface;   an interconnect structure disposed along the front-side surface of the substrate, wherein the interconnect structure comprises a plurality of conductive wires, a plurality of conductive vias, and a first absorption structure;   a first image sensor element disposed within the substrate and configured to generate electrical signals from an electromagnetic radiation within a first range of wavelengths; and   a second image sensor element disposed within the substrate and configured to generate electrical signals from the electromagnetic radiation within a second range of wavelengths that is different than the first range of wavelengths, wherein the second image sensor element is laterally adjacent to the first image sensor element;   wherein the first image sensor element overlies the first absorption structure and is spaced laterally between opposing sidewalls of the first absorption structure.   
     
     
         2 . The image sensor device of  claim 1 , wherein when viewed from above, an area of the first absorption structure is greater than an area of the first image sensor element. 
     
     
         3 . The image sensor device of  claim 1 , further comprising:
 a third image sensor element disposed within the substrate and configured to generate electrical signals from the electromagnetic radiation within the first range of wavelengths, wherein the third image sensor element is laterally adjacent to the first image sensor element; and   a second absorption structure underlying the third image sensor element, wherein a sidewall of the second absorption structure abuts a sidewall of the first absorption structure.   
     
     
         4 . The image sensor device of  claim 1 , wherein the first absorption structure is configured to interact with the electromagnetic radiation within the first range of wavelengths, and wherein the first range of wavelengths comprises near infrared (NIR) radiation. 
     
     
         5 . The image sensor device of  claim 1 , wherein the first absorption structure comprises titanium nitride, tantalum nitride, and/or tungsten. 
     
     
         6 . The image sensor device of  claim 1 , wherein a top surface of the first absorption structure is aligned with a top surface of a first layer of the plurality of conductive wires. 
     
     
         7 . The image sensor device of  claim 1 , wherein the first absorption structure and the plurality of conductive wires respectively comprise a conductive liner and a conductive body. 
     
     
         8 . The image sensor device of  claim 1 , wherein the first absorption structure is disposed between the plurality of conductive wires and the front-side surface of the substrate. 
     
     
         9 . An integrated chip, comprising:
 a substrate comprising a front-side surface opposite a back-side surface;   a plurality of pixel devices disposed on the front-side surface of the substrate;   an interconnect structure disposed along the front-side surface of the substrate, wherein the interconnect structure comprises a plurality of conductive wires and a plurality of conductive vias disposed within an interconnect dielectric structure and electrically coupled to the plurality of pixel devices;   a plurality of pixel sensors disposed within the substrate, wherein the plurality of pixel sensors respectively comprise a first image sensor element and a second image sensor element, wherein the first image sensor element is configured to generate electrical signals from infrared (IR) radiation and the second image sensor element is configured to generate electrical signals from visible light; and   a plurality of absorption structures disposed within the interconnect dielectric structure and below the plurality of pixel sensors, wherein the first image sensor elements are respectively laterally spaced between opposing sidewalls of a corresponding absorption structure, and wherein the second image sensor elements are laterally offset from the plurality of absorption structures by a non-zero distance.   
     
     
         10 . The integrated chip of  claim 9 , wherein the plurality of pixel sensors comprises a first pixel sensor and a second pixel sensor, wherein the first image sensor element of the first pixel sensor is laterally adjacent to the first image sensor element of the second pixel sensor. 
     
     
         11 . The integrated chip of  claim 9 , wherein the second image sensor element continuously extends from a first sidewall of the first image sensor element to a second sidewall of the first image sensor element, wherein the first sidewall is perpendicular to the second sidewall. 
     
     
         12 . The integrated chip of  claim 9 , wherein the plurality of absorption structures are electrically coupled to the plurality of pixel devices by way of the plurality of conductive vias. 
     
     
         13 . The integrated chip of  claim 9 , wherein the plurality of absorption structures are spaced vertically between the plurality of pixel sensors and the plurality of conductive wires. 
     
     
         14 . The integrated chip of  claim 9 , wherein the interconnect dielectric structure directly contacts a bottom surface of each absorption structure across an entirety of the bottom surface and directly contacts a top surface of each absorption structure across an entirety of the top surface. 
     
     
         15 . The integrated chip of  claim 9 , further comprising:
 an isolation structure disposed from the back-side surface of the substrate to a point below the back-side surface, wherein the isolation structure is disposed laterally between the first image sensor element and the second image sensor element of each pixel sensor; and   wherein the absorption structures respectively laterally extends between corresponding opposing sidewalls of the isolation structure.   
     
     
         16 . The integrated chip of  claim 15 , wherein the isolation structure comprises a passivation layer and a trench layer, wherein the passivation layer is disposed between the trench layer and the substrate, and wherein the trench layer comprises a conductive material. 
     
     
         17 . The integrated chip of  claim 9 , further comprising:
 a light filter array disposed over the front-side surface of the substrate, wherein the light filter array comprises a first light filter overlying the first image sensor element and a second light filter overlying the second image sensor element, wherein the first light filter is configured to pass IR radiation and block visible light, and wherein the second light filter is configured to pass visible light and block IR radiation.   
     
     
         18 . The integrated chip of  claim 17 , wherein the second light filter comprises a color filter overlying a band pass filter. 
     
     
         19 - 20 . (canceled) 
     
     
         21 . An integrated chip, comprising:
 a plurality of pixel sensors disposed within a substrate, wherein the plurality of pixel sensors respectively comprise a first image sensor element adjacent to a second image sensor element, wherein the first image sensor element of the pixel sensors meet at a center of the plurality of pixel sensors, wherein the plurality of pixel sensors comprises a first pixel sensor adjacent to a second pixel sensor;   a first absorption structure directly underlying the first image sensor element of the first pixel sensor; and   a second absorption structure directly underlying the second image sensor element of the second pixel sensor, wherein the first absorption structure directly contacts the second absorption structure.   
     
     
         22 . The integrated chip of  claim 21 , further comprising:
 a grid structure overlying the substrate, wherein the first image sensor element of the first pixel sensor is spaced between a first pair of opposing sidewalls of the grid structure, wherein the first absorption structure directly underlies both sidewalls in the first pair of opposing sidewalls.