Providing code sections for matrix of arithmetic logic units in a processor

Abstract

The present invention relates to a processor having a trace cache and a plurality of ALUs arranged in a matrix, comprising an analyser unit located between the trace cache and the ALUs, wherein the analyser unit analyses the code in the trace cache, detects loops, transforms the code, and issues to the ALUs sections of the code combined to blocks for joint execution for a plurality of clock cycles.

1 . (canceled) 
     
     
         2 . A data processor comprising:
 an execution stage for processing data having a plurality of ALUs in a multidimensional array, adapted to process data according to instructions that are issued thereto, with at least some of the plurality of ALUs at least having an operand data input and a result data output, and the multidimensional array having a data network at least interconnecting the at least some of the plurality of ALUs for providing operand data to the at least some of the plurality of ALUs, result data generated by the at least some of the plurality of ALUs when executing amended instructions issued thereto being provided to the data network;   an instruction fetch unit to fetch instructions,
 at least some of the instructions fetched by said instruction fetch unit being executable to process operand data to produce result data, wherein the operand data has at least one operand source register reference and the result data has at least one target register reference, and 
 the at least some of the instructions forming a sequence of instructions, wherein at least some of the result data produced in response to preceding instructions in the sequence of instructions is used as operand data in succeeding instructions in the sequence of instructions; 
   an instruction issue unit to issue amended instructions at least to the execution stage, for executing at least some of the amended instructions by at least some of the plurality of ALUs,
 the at least some of the plurality of ALUs generating the result data from the operand data by execution of the at least some of amended instructions issued by the instruction issue unit; and 
   an instruction amendment unit comprising
 a register cross referencing table that cross-references target register references of the fetched instructions to the ALUs in the multidimensional array producing the result data corresponding to said target register references of the fetched instructions, 
 wherein, for instructions of the sequence of instructions that use result data generated in response to preceding instructions as operand data, the instruction amendment unit is adapted to look up, in the register cross referencing table, the ALUs in the multidimensional array that execute the respective preceding instructions that generate the result data corresponding to said target register references of the fetched instructions, 
 the instruction amendment unit generating amended instructions and providing the amended instructions to the instruction issue unit, the instruction amendment unit generating the amended instructions based on the fetched sequence of instructions and based on the result of the look-up, 
 such that when the amended instructions are issued by the instruction issue unit and executed by the execution stage, the result data generated by ALUs executing preceding instructions issued by the instruction issue unit are transferred in the data network in a manner enabling the use thereof as operand data in the succeeding instructions issued by the instruction issue unit. 
   
     
     
         3 . The data processor according to  claim 2 , wherein the execution stage comprises a number of referenceable registers for data, wherein the referenceable registers are:
 usable as the operand data to be processed by the at least some of the plurality of ALUs and as the result data generated by the at least some of the plurality of ALUs when executing the instructions issued thereto by the instruction issue unit; and   connectable to the data network to at least temporarily store the result data to be used as the operand data in one or more of the succeeding instructions.   
     
     
         4 . The data processor according to  claim 3 , wherein the instruction amendment unit generates and adds data network connection configuration information to the amended instructions. 
     
     
         5 . The data processor according to  claim 4 , wherein the instruction issue unit is adapted to issue the data network connection configuration information for the data network. 
     
     
         6 . The data processor according to  claim 3 , wherein one or more of the at least some of the plurality of ALUs have at least two operand data inputs, and wherein the instruction amendment unit is adapted to amend the instructions by defining one of the at least two operand data inputs as a specific operand data input. 
     
     
         7 . The data processor according to  claim 2 , wherein when processing an instruction loop, the instructions issued to the plurality of ALUs remain temporarily fixed for a plurality of clock cycles while a plurality of data words flows through the plurality of ALUs. 
     
     
         8 . The data processor according to  claim 7 , wherein each of the plurality of data words is processed by the plurality of ALUs based on the temporarily fixed instructions. 
     
     
         9 . The data processor according to  claim 8 , wherein when the instruction loop has terminated, operation of the data processor continues with one or more newly-fetched and issued instructions. 
     
     
         10 . The data processor according to  claim 7 , wherein the execution stage comprises
 at least one load unit to load operand data from a memory and provide the loaded operand data to the data network; and   at least one store unit to store result data provided by the data network to said memory.   
     
     
         11 . The data processor according to  claim 2 , wherein the data processor is a graphics processor. 
     
     
         12 . The data processor according to  claim 2 , wherein the data processor is Field Programmable Gate Array. 
     
     
         13 . A method comprising:
 fetching instructions using an instruction fetch unit,
 at least some of the instructions fetched by said instruction fetch unit being executable, when issued thereto, by a plurality of ALUs in a multidimensional array of an execution stage to process operand data to produce result data, wherein the operand data has at least one operand source register reference and the result data has at least one target register reference, and 
 the at least some of the instructions forming a sequence of instructions, wherein at least some of the result data produced in response to executing preceding instructions in the sequence of instructions is used as operand data in executing succeeding instructions in the sequence of instructions; 
 providing the operand data to at least some of the plurality of ALUs using a data network of the multidimensional array that interconnects the plurality of ALUs, wherein the result data generated by the at least some of the plurality of ALUs when executing the instructions are provided to the data network; and 
   accessing, using an instruction amendment unit, a register cross referencing table that cross references target register references of the fetched instructions to the ALUs in the multidimensional array producing the result data corresponding to said target register references of the fetched instructions,
 wherein, for instructions of the sequence of instructions that use result data generated in response to preceding instructions as operand data, accessing the register cross referencing table includes looking up, in the register cross referencing table, the ALUs in the multidimensional array that execute the respective preceding instructions that generate the result data corresponding to said target register references of the fetched instructions; 
   generating, using the instruction amendment unit, amended instructions based on the fetched sequence of instructions and based on the result of the look-up;   providing, by the instruction amendment unit, the amended instructions to an instruction issue unit;   issuing, by the instruction issue unit, amended instructions at least to the execution stage; and   executing at least some of the amended instructions issued by the instruction issue unit by at least some of the plurality of ALUs of the execution stage, wherein the at least some of the plurality of ALUs have at least an operand data input and a result data output, wherein the at least some of the plurality of ALUs generate the result data from the operand data by execution of the at least some of amended instructions issued by the instruction issue unit,   such that when the amended instructions are issued by the instruction issue unit and executed by the execution stage, the result data generated by ALUs executing preceding instructions issued by the issue unit are transferred in the data network in a manner enabling the use thereof as operand data in the succeeding issued by the issue unit.   
     
     
         14 . The method according to  claim 13 , wherein the execution stage comprises a number of referenceable registers for data, wherein the method further comprises:
 using the referenceable registers as operand data to be processed by the at least some of the plurality of ALUs and as the result data generated by the at least some of the plurality of ALUs when executing the instructions issued thereto by the instruction issue unit; and   connecting, at least temporarily, the referenceable registers to the data network to store the result data to be used as the operand data in one or more of the succeeding instructions.   
     
     
         15 . The method according to  claim 14 , further comprising generating and adding, using the instruction amendment unit, data network connection configuration information to the amended instructions. 
     
     
         16 . The method according to  claim 15 , further comprising issuing, by the instruction issue unit, the data network connection configuration information for the data network. 
     
     
         17 . The method according to  claim 14 , wherein one or more of the at least some of the plurality of ALUs have at least two operand data inputs, and further comprising amending the instructions, using the instruction amendment unit, by defining one of the at least two operand data inputs as a specific operand data input. 
     
     
         18 . The method according to  claim 13 , further comprising, when processing an instruction loop, temporarily fixing the instructions issued to the plurality of ALUs for a plurality of clock cycles while a plurality of data words flows through the plurality of ALUs. 
     
     
         19 . The method according to  claim 18 , wherein each of the plurality of data words is processed by the plurality of ALUs based on the temporarily fixed instructions. 
     
     
         20 . The method according to  claim 19 , further comprising, after the instruction loop has terminated, continuing operation of the method by repeating the fetching, the providing the operand data, the accessing the register cross referencing table, the generating, the providing the amended instructions, the issuing, and the executing with one or more newly-fetched and issued instructions. 
     
     
         21 . The method according to  claim 18 , wherein the execution stage comprises:
 at least one load unit to load operand data from a memory and provide the loaded operand data to the data network; and   at least one store unit to store result data provided by the data network to said memory.