Fault buffer for tracking page faults in unified virtual memory system

Abstract

A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.

What is claimed is: 
     
         1 . A computer system, comprising:
 a first processor;   a system memory that is coupled to the first processor and includes a page state directory, wherein the page state director includes a plurality of virtual address-to-physical address mappings for a plurality of memory pages that are accessible via a virtual memory address space;   a second processor; and   a local memory that is coupled to the second processor and includes a page table, wherein the page table includes one or more virtual address-to-physical address mappings for one or more memory pages included in the plurality of memory pages to which the second processor has access.   
     
     
         2 . The computer system of  claim 1 , wherein an application, when executed by the first processor, can access any memory page included in the plurality of memory pages via a pointer that points to different virtual addresses across the virtual memory address space. 
     
     
         3 . The computer system of  claim 1 , wherein the system memory further includes another page table that includes one or more virtual address-to-physical address mappings for one or more memory pages included in the plurality of memory pages to which the first processor has access. 
     
     
         4 . The computer system of  claim 3 , wherein a page fault is issued when the first processor attempts to access a first memory page that is included in the plurality of memory pages but is not included in the one or more memory pages to which the first processor has access. 
     
     
         5 . The computer system of  claim 4 , wherein the first memory page is migrated from the local memory to the system memory as part of a page fault sequence to provide the first processor with access to the first memory page. 
     
     
         6 . The computer system of  claim 5 , wherein a first entry is generated for the another page table as part of the page fault sequence, wherein the first entry indicates that the first processor has access to the first memory page. 
     
     
         7 . The computer system of  claim 5 , wherein a first entry that is included in the page state directory and corresponds to the first memory page is updated as part of the page fault sequence to reflect that the first memory page is accessible to both the first processor and the second processor. 
     
     
         8 . The computer system of  claim 5 , wherein a first entry that is included in the page state directory and corresponds to the first memory page is updated as part of the page fault sequence to reflect that the first memory page is accessible to only the first processor. 
     
     
         9 . The computer system of  claim 1 , wherein a page fault is issued when the second processor attempts to access a first memory page that is included in the plurality of memory pages but is not included in the one or more memory pages to which the second processor has access. 
     
     
         10 . The computer system of  claim 9 , wherein a first entry is generated for the page table as part of a page fault sequence to provide the second processor with access to the first memory page, wherein the first entry indicates that the second processor has access to the first memory page. 
     
     
         11 . The computer system of  claim 10 , wherein a first entry that is included in the page state directory and corresponds to the first memory page is updated as part of the page fault sequence to reflect that the first memory page is accessible to both the first processor and the second processor. 
     
     
         12 . The computer system of  claim 11 , wherein the first memory page is stored in the system memory. 
     
     
         13 . The computer system of  claim 10 , wherein a first entry that is included in the page state directory and corresponds to the first memory page is updated as part of the page fault sequence to reflect that the first memory page is accessible to only the second processor. 
     
     
         14 . The computer system of  claim 13 , wherein the first memory page is migrated from the system memory to the local memory as part of the page fault sequence. 
     
     
         15 . The computer system of  claim 1 , wherein the page state directory includes a separate entry for each memory page included in the plurality of memory pages, and each separate entry includes a virtual memory-to-physical memory mapping for a corresponding memory page included in the plurality of memory pages. 
     
     
         16 . The computer system of  claim 1 , wherein the page state directory includes a first entry that corresponds to a first memory page included in one or more memory pages to which the first processor has access, and an ownership state for the first memory page comprises a CPU-owned ownership state indicating that only the first processor has access to the first memory page. 
     
     
         17 . The computer system of  claim 16 , wherein the first memory page is stored in the system memory. 
     
     
         18 . The computer system of  claim 1 , wherein the page state directory includes a first entry that corresponds to a first memory page included in one or more memory pages to which the first processor has access, and an ownership state for the first memory page comprises a CPU-shared ownership state indicating that both the first processor and the second processor have access to the first memory page. 
     
     
         19 . The computer system of  claim 18 , wherein the first memory page is also included in the one or more memory pages to which the second processor has access. 
     
     
         20 . The computer system of  claim 18 , wherein the first memory page is stored in the system memory. 
     
     
         21 . The computer system of  claim 1 , wherein the page state directory includes a first entry that corresponds to a first memory page included in the one or more memory pages to which the second processor has access, and an ownership state for the first memory page comprises a PPU-owned ownership state indicating that only the second processor has access to the first memory page. 
     
     
         22 . The computer system of  claim 21 , wherein the first memory page is stored in the local memory. 
     
     
         23 . The computer system of  claim 1 , wherein the page state directory includes a first entry that corresponds to a first memory page included in the one or more memory pages to which the second processor has access, and an ownership state for the for the first memory page comprises a PPU-shared ownership state indicating that both the first processor and the second processor have access to the first memory page. 
     
     
         24 . The computer system of  claim 23 , where the first memory page is stored in the local memory. 
     
     
         25 . The computer system of  claim 1 , wherein the first processor comprises a central processing unit, and the second processor comprises a parallel processing unit. 
     
     
         26 . The computer system of  claim 25 , wherein the parallel processing unit comprises a graphics processing unit. 
     
     
         27 . A computer-implemented method for accessing memory pages, the method comprising:
 receiving a memory access request for a first memory page, wherein the memory access request includes a first virtual memory address,   determining either that the first memory page is not stored in a system memory coupled to a first processor based on the first virtual memory address and a first page table associated with the first processor, the first page table including one or more virtual address-to-physical address mappings for one or more memory pages to which the first processor has access, or that the first memory page is not stored in a local memory coupled to a second processor based on the first virtual memory address and a second page table associated with the second processor, the second page table including one or more virtual address-to-physical address mappings for one or more memory pages to which the second processor has access;   in response to determining that the first memory page is either not stored in the system memory or not stored in the local memory, generating a page fault; and   in response to the page fault, executing a page fault sequence using a page state directory to provide at least one of the first processor or the second processor access to the first memory page, wherein the page state director includes a plurality of virtual address-to-physical address mappings for a plurality of memory pages that includes both the one or more memory pages to which the first processor has access and the one or more memory pages to which the second processor has access.   
     
     
         28 . The computer-implemented method of  claim 27 , wherein an application executing on the first processor can access any memory page included in the plurality of memory pages via a pointer that points to different virtual addresses across a virtual memory address space. 
     
     
         29 . The computer-implemented method of  claim 27 , wherein the first memory page is stored in the system memory, and executing the page fault sequence comprises providing the second processor with access to the first memory page while the first memory page remains in the system memory. 
     
     
         30 . The computer-implemented method of  claim 27 , wherein the first memory page is stored in the system memory, and executing the page fault sequence comprises moving the first memory page from the system memory to the local memory. 
     
     
         31 . The computer-implemented method of  claim 27 , wherein the first memory page is stored in the local memory, and executing the page fault sequence comprises moving the first memory page from the local memory to the system memory.