One-time programmable memory unit cell

Abstract

A one-time programmable memory unit cell includes a substrate comprising thereon a first active area and a second active area isolated from the first active area, a read select transistor disposed on the first active area, a data storage transistor disposed on the first active area and serially connected to the read select transistor, and a program select transistor disposed on the second active area. During read operation, the state “1” bit current is the transistor “on” current, while the state “0” bit current is the transistor “off” current.

What is claimed is: 
     
         1 . A one-time programmable memory unit cell, comprising:
 a substrate comprising thereon a first active area and a second active area isolated from the first active area;   a read select transistor disposed on the first active area, wherein the read select transistor comprises a first gate, a first gate dielectric layer between the first gate and the substrate, a first drain region in the substrate on one side of the first gate, and a first source region in the substrate on an opposing side of the first gate;   a data storage transistor disposed on the first active area and serially connected to the read select transistor, wherein the data storage transistor comprises a second gate, a second gate dielectric layer between the second gate and the substrate, a second drain region in the substrate on one side of the second gate, a second source region in the substrate on an opposing side of the second gate, and a channel region between the second drain region and the second source region, wherein the second drain region merges with the first source region of the read select transistor, wherein the second gate comprises a main gate portion directly above the channel region, a first extension gate portion and a second extension gate portion on two opposite sidewalls of the main gate portion, respectively, wherein the main gate portion, the first extension gate portion and the second extension gate portion constitute a gate electrode of the data storage transistor, and wherein the second gate dielectric layer comprises a first portion between the drain region and the first extension gate portion, a second portion between the channel region and the main gate portion, and a third portion between the source region and the second extension gate portion, wherein the first portion and the third portion are thinner than the second portion; and   a program select transistor disposed on the second active area, wherein the program select transistor comprises a third gate, a third gate dielectric layer between the third gate and the substrate, a third drain region in the substrate on one side of the third gate, and a third source region in the substrate on the other side of the third gate, wherein the third drain region is electrically coupled to the second gate of the data storage transistor.   
     
     
         2 . The one-time programmable memory unit cell according to  claim 1  further comprising:
 a first dielectric spacer and a second dielectric spacer on the first extension gate portion and the second extension gate portion, respectively. 
 
     
     
         3 . The one-time programmable memory unit cell according to  claim 2 , wherein the first dielectric spacer and the second dielectric spacer are situated directly on the first portion and the third portion of the gate dielectric layer, respectively. 
     
     
         4 . The one-time programmable memory unit cell according to  claim 1 , wherein the first extension gate portion of the gate electrode is situated directly on the first portion of the gate dielectric layer and the second extension gate portion of the gate electrode is situated directly on the third portion of the gate dielectric layer. 
     
     
         5 . The one-time programmable memory unit cell according to  claim 1  further comprising:
 a first vertical PN junction disposed between the drain region and the channel region and proximate to a top surface of the substrate, wherein the first vertical PN junction is situated directly underneath the main gate portion of the gate electrode; and 
 a second vertical PN junction disposed between the source region and the channel region and proximate to the top surface of the substrate, wherein the second vertical PN junction is situated directly underneath the main gate portion of the gate electrode. 
 
     
     
         6 . The one-time programmable memory unit cell according to  claim 1 , wherein the first gate, the second gate, and the third gate comprise a single polysilicon layer or a metal gate. 
     
     
         7 . The one-time programmable memory unit cell according to  claim 1 , wherein the data storage transistor has a gate-to-source/drain breakdown voltage lower than a gate-to-channel breakdown voltage and a gated source/drain junction breakdown voltage. 
     
     
         8 . The one-time programmable memory unit cell according to  claim 1 , wherein the substrate is a P type silicon substrate, wherein the first drain region, the first source region, the second drain region, the second source region, the third drain region, and the third source region are N +  doping regions. 
     
     
         9 . The one-time programmable memory unit cell according to  claim 8 , wherein the program select transistor is constructed on a triple well structure comprising a deep N well in the P type silicon substrate and a P well isolated from the P type silicon substrate by the deep N well. 
     
     
         10 . The one-time programmable memory unit cell according to  claim 1 , wherein the substrate comprises a silicon-on-insulator (SOI) substrate. 
     
     
         11 . The one-time programmable memory unit cell according to  claim 1 , wherein the third source region is electrically coupled to ground. 
     
     
         12 . The one-time programmable memory unit cell according to  claim 1 , wherein the second active area is disposed in close proximately to the first active area.