Device, method and system for transparently changing a frequency of an interconnect fabric

Abstract

Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.

What is claimed is: 
     
         1 . A processor apparatus, comprising:
 a controller unit to receive a first signal comprising an indication of a need to perform a power state transition with the processor, and log a time t 0  of a communication of the first signal; and   a power management unit coupled to receive from the controller unit a second signal based on the indication. The power management unit to perform a wake-up operation in response to the second signal, determine the time t 0  from the controller unit after the wake-up operation, and based on the time t 0 , to generate an output comprising an identifier of a latency of the power state transition.   
     
     
         2 . The apparatus of  claim 1 , wherein the power management unit is further to perform one or more operations of the power state transition after a receipt of the indication of the time t 0  from the controller unit. 
     
     
         3 . The apparatus of  claim 2 , wherein the power management unit is to compute a duration of the latency based on the indication of the time t 0 , wherein the latency comprises a first period of time from the time t 0  to a transmission of the second signal from the controller unit. 
     
     
         4 . The apparatus of  claim 3 , wherein the power management unit is to request the indication of the time t 0 , wherein in doing so, the power management unit is to send a query to the controller unit, and wherein the latency further comprises a second period of time during the wake-up operation, and before a communication of the query. 
     
     
         5 . The apparatus of  claim 4 , wherein the latency further comprises a third period of time from the communication of the query to a communication of the indication of the time t 0  to the power management unit. 
     
     
         6 . The apparatus of  claim 5 , wherein, the latency further comprises a fourth period of time after the communication of the indication of the time t 0  to the power management unit. 
     
     
         7 . The apparatus of  claim 1 , wherein the power management unit is to send a query to the controller unit to request the indication of the time t 0 , and wherein the controller unit, based on the query, is to calculate a total time between the time t 0  and a time of a communication of the query. 
     
     
         8 . The apparatus of  claim 1 , wherein the power state transition includes a transition of the processor from a first power state which is to disable an execution of software to a second power state which is to enable the execution of software. 
     
     
         9 . A system, comprising:
 a processor including:
 first circuitry to detect a need to perform a power state transition with the processor, 
 second circuitry coupled to receive from the first circuitry a signal which indicates the need, wherein based on the signal, the second circuitry is to log a time t 0  of a communication of the signal, and to generate a control signal, and 
 third circuitry, coupled to the second circuitry, to initiate a wake-up operation in response to the control signal, request an indication of the time t 0  from the second circuitry after the wake-up operation, and provide to an operating system a communication comprising a value, based on the indication of the time t 0 , identifying a latency of the power state transition; and 
   a display device coupled to the processor, the display device to display an image based on a signal communicated with the processor.   
     
     
         10 . The system of  claim 9 , wherein the third circuitry is to perform one or more operations of the power state transition after a receipt of the indication of the time t 0  from the second circuitry. 
     
     
         11 . The system of  claim 9 , wherein the third circuitry is to compute a duration of the latency based on the indication of the time t 0 , wherein the latency comprises a first period of time from the time t 0  to a transmission of the control signal from the second circuitry. 
     
     
         12 . The system of  claim 11 , wherein the third circuitry is to request the indication of the time t 0 , the request includes the third circuitry to send a query to the second circuitry, and wherein the latency further comprises a second period of time during the wake-up operation, and before a communication of the query. 
     
     
         13 . The system of  claim 12 , wherein the latency further comprises a third period of time from the communication of the query to a communication of the indication of the time t 0  to the third circuitry. 
     
     
         14 . The system of  claim 13 , wherein the latency further comprises a fourth period of time after the communication of the indication of the time t 0  to the third circuitry. 
     
     
         15 . The system of  claim 9 , wherein the third circuitry is to send a query to the second circuitry to request the indication of the time t 0 , and wherein the second circuitry, based on the query, is to calculate a total time between the time t 0  and a time of a communication of the query. 
     
     
         16 . The system of  claim 9 , wherein the power state transition includes a transition of the processor from a first power state which disables an execution of software to a second power state which enables the execution of software. 
     
     
         17 . A method, comprising:
 at a first processor circuit:
 receiving a signal which indicates a need to perform a power state transition with the processor, 
 logging a time t 0  of a communication of the signal, and 
 generating a control signal based on the signal; and 
 at a second processor circuit: 
 initiating a wake-up operation in response to the control signal, 
 requesting an indication of the time t 0  from the first circuit after the wake-up operation, and 
 providing to an operating system a communication comprising a value, based on the indication of the time t 0  that identifies a latency of the power state transition. 
   
     
     
         18 . The method of  claim 17 , wherein the second circuit is to further perform one or more operations of the power state transition after a receipt of the indication of the time t 0  from the first circuit. 
     
     
         19 . The method of  claim 17 , wherein the second circuit is to compute a duration of the latency based on the indication of the time t 0 , wherein the latency comprises a first period of time from the time t 0  to a transmission of the control signal from the first circuit. 
     
     
         20 . The method of  claim 19 , wherein requesting the indication of the time t 0  comprises the second circuit sending a query to the first circuit, and wherein the latency further comprises a second period of time during the wake-up operation and before the sending of the query.