Vector load and duplicate operations

Abstract

Disclosed embodiments relate to methods of using a processor to load and duplicate scalar data from a source into a destination register. The data may be duplicated in byte, half word, word or double word parts, according to a duplication pattern.

1 . A system comprising:
 a source vector register;   a destination vector register having a register size; and   a processor configured to:
 receive a duplication instruction including first information specifying the source vector register, second information specifying a destination vector register, and third information specifying a size of a first data element in the source vector register; and 
 execute the duplication instruction to cause the first data element to be loaded into the destination vector register a number of times equal to the register size of destination vector register divided by the size of the first data element. 
   
     
     
         2 . The system of  claim 1 ,
 wherein the third information occupies a less significant position in the duplication instruction than the first information, and   wherein the third information occupies a less significant position in the duplication instruction than the second information.   
     
     
         3 . The system of  claim 1 ,
 wherein the third information includes two bits in the duplication instruction, and   wherein the two bits specify the size of the first data element.   
     
     
         4 . The system of  claim 1 , wherein the third information specifies the size of the first data element by specifying a byte, a half-word, a word, or a double word. 
     
     
         5 . The system of  claim 1 , wherein a first value of the third information specifies a byte length for the size of the first data element. 
     
     
         6 . The system of  claim 5 , wherein a second value of the third information specifies a half-word length for the size of the first data element. 
     
     
         7 . The system of  claim 6 , wherein a third value of the third information specifies a word length for the size of the first data element. 
     
     
         8 . The system of  claim 7 , wherein a fourth value of the third information specifies a double-word length for the size of the first data element. 
     
     
         9 . The system of  claim 1 , wherein to execute the duplication instruction, the processor is configured to cause the first data element to be loaded into consecutive locations in the destination vector register the number of times equal to the register size of the destination vector register divided by the size of the first data element. 
     
     
         10 . The system of  claim 1 , wherein a register size of the source vector register is equal to the register size of the destination vector register. 
     
     
         11 . The system of  claim 1 ,
 wherein the source vector register is operable to store a plurality of data elements, and   wherein the destination vector register is operable to store a plurality of data elements.   
     
     
         12 . A method comprising:
 receiving, in a processor, a duplication instruction including first information specifying a source vector register, second information specifying a destination vector register, and third information specifying a size of a first data element in the source vector register, wherein the destination vector register has a register size; and   executing the duplication instruction using the processor to cause the first data element to be loaded into the destination vector register a number of times equal to the register size of destination vector register divided by the size of the first data element.   
     
     
         13 . The method of  claim 12 ,
 wherein the third information occupies a less significant position in the duplication instruction than the first information, and   wherein the third information occupies a less significant position in the duplication instruction than the second information.   
     
     
         14 . The method of  claim 12 ,
 wherein the third information includes two bits in the duplication instruction, and   wherein the two bits specify the size of the first data element.   
     
     
         15 . The method of  claim 12 , wherein the third information specifies the size of the first data element by specifying a byte, a half-word, a word, or a double word. 
     
     
         16 . The method of  claim 12 , wherein executing the duplication instruction causes the first data element to be loaded into consecutive locations in the destination vector register the number of times equal to the register size of the destination vector register divided by the size of the first data element. 
     
     
         17 . The method of  claim 12 , wherein a register size of the source vector register is equal to the register size of the destination vector register. 
     
     
         18 . The method of  claim 12 ,
 wherein the source vector register is operable to store a plurality of data elements, and   wherein the destination vector register is operable to store a plurality of data elements.   
     
     
         19 . A system comprising:
 a source vector register having a first register size and operable to store a first plurality of data elements;   a destination vector register having a second register size operable to store a second plurality of data elements, wherein the first register size is equal to the second register size; and   a processor configured to:
 receive a duplication instruction including first information specifying the source vector register, second information specifying a destination vector register, and third information specifying a size of a first data element in the source vector register; and 
 execute the duplication instruction to cause the first data element to be loaded into consecutive locations in the destination vector register a number of times equal to the register size of destination vector register divided by the size of the first data element. 
   
     
     
         20 . The system of  claim 19 ,
 wherein a first value of the third information specifies a half-word length for the size of the first data element, and   wherein a second value of the third information specifies a word length for the size of the first data element.