Tag processing for external caches

Abstract

A device includes a cache memory and a memory controller coupled to the cache memory. The memory controller is configured to receive a first read request from a cache controller over an interconnect, the first read request comprising first tag data identifying a first cache line in the cache memory, and determine that the first read request comprises a tag read request. The memory controller is further configured to read second tag data corresponding to the tag read request from the cache memory, compare the second tag data read from the cache memory to the first tag data received from the cache controller with the first read request, and if the second tag data matches the first tag data, initiate an action with respect to the first cache line in the cache memory.

1 . (canceled) 
     
     
         2 . A memory module comprising:
 a main memory storing data;   a cache memory to store at least a portion of the data from the main memory, the cache memory comprising a plurality of sets of cache lines each comprising a plurality of cache storage locations; and   a memory controller coupled to the cache memory, wherein the memory controller is configured to:
 compare first tag data from a received read request to second tag data from the cache memory, wherein the first tag data identifies a first cache line in a first set of cache lines in the cache memory, wherein the second tag data is stored in a second cache line of a second set of cache lines in the cache memory, and wherein the second set of cache lines is different than the first set of cache lines; and 
 if the second tag data matches the first tag data, initiate an action with respect to the first cache line in the cache memory. 
   
     
     
         3 . The memory module of  claim 2 , wherein the cache memory comprises a set associative cache implemented on a dynamic random access memory (DRAM) device. 
     
     
         4 . The memory module of  claim 2 , wherein the read request comprises a tag read request identified by a corresponding identifier. 
     
     
         5 . The memory module of  claim 2 , wherein the memory controller is further configured to:
 send the second tag data read from the cache memory to a cache controller coupled to the memory module over an interconnect.   
     
     
         6 . The memory module of  claim 2 , wherein to initiate the action with respect to the first cache line, the memory controller is configured to:
 prepare a portion of the cache memory corresponding to the first cache line for a second read request to be subsequently received from a cache controller.   
     
     
         7 . The memory module of  claim 2 , wherein to initiate the action with respect to the first cache line, the memory controller is configured to:
 read the first cache line from the cache memory before a second read request is received from a cache controller.   
     
     
         8 . The memory module of  claim 7 , wherein to initiate the action with respect to the first cache line, the memory controller is further configured to:
 send the first cache line to the cache controller without receiving the second read request from the cache controller.   
     
     
         9 . The memory module of  claim 7 , wherein to initiate the action with respect to the first cache line, the memory controller is further configured to:
 receive the second read request from the cache controller; and   send the first cache line to the cache controller.   
     
     
         10 . The memory module of  claim 2 , wherein the memory controller is further configured to:
 if the second tag data does not match the first tag data, return an indication of a cache miss to a cache controller.   
     
     
         11 . A method comprising:
 comparing, by a memory controller of a memory module, first tag data from a received read request to second tag data from a cache memory of the memory module, wherein the first tag data identifies a first cache line in a first set of cache lines in the cache memory, wherein the second tag data is stored in a second cache line of a second set of cache lines in the cache memory, and wherein the second set of cache lines is different than the first set of cache lines; and   if the second tag data matches the first tag data, initiating an action with respect to the first cache line in the cache memory.   
     
     
         12 . The method of  claim 11 , wherein the cache memory comprises a set associative cache implemented on a dynamic random access memory (DRAM) device. 
     
     
         13 . The method of  claim 11 , further comprising:
 sending the second tag data read from the cache memory to a cache controller coupled to the memory module over an interconnect.   
     
     
         14 . The method of  claim 11 , wherein the read request comprises a tag read request identified by a corresponding identifier. 
     
     
         15 . The method of  claim 11 , wherein initiating the action with respect to the first cache line comprises:
 preparing a portion of the cache memory corresponding to the first cache line for a second read request to be subsequently received from a cache controller.   
     
     
         16 . The method of  claim 11 , wherein initiating the action with respect to the first cache line comprises:
 reading the first cache line from the cache memory before a second read request is received from a cache controller.   
     
     
         17 . The method of  claim 16 , wherein initiating the action with respect to the first cache line further comprises:
 sending the first cache line to the cache controller without receiving the second read request from the cache controller.   
     
     
         18 . The method of  claim 16 , wherein initiating the action with respect to the first cache line further comprises:
 receiving the second read request from the cache controller; and   sending the first cache line to the cache controller.   
     
     
         19 . The method of  claim 11 , further comprising:
 if the second tag data does not match the first tag data, returning an indication of a cache miss to a cache controller.   
     
     
         20 . A device comprising:
 a cache memory comprising a plurality of sets of cache lines each comprising a plurality of cache storage locations; and   a memory controller coupled to the cache memory, wherein the memory controller is configured to:
 compare first tag data from a received write request to second tag data from the cache memory, wherein the first tag data identifies a first cache line in a first set of cache lines in the cache memory, wherein the second tag data is stored in a second cache line of a second set of cache lines in the cache memory, and wherein the second set of cache lines is different than the first set of cache lines; 
 if the second tag data matches the first tag data and the first cache line is not already marked as dirty, modify a dirty status indicator for the first cache line before a second write request is received from a cache controller coupled to the device over an interconnect; 
 receive the second write request is received from the cache controller over the interconnect; and 
 perform a write operation on the first cache line. 
   
     
     
         21 . The device of  claim 20 , wherein the memory controller is further configured to:
 if the second tag data does not match the first tag data, send at least one of the second tag data read from the cache memory or an indication of a cache miss to the cache controller.