Semiconductor Device

Abstract

A semiconductor device includes “n” pairs of pn-junction structures, wherein the i-th pair includes two pn-junction structures of the i-th type, wherein the two pn-junction structures of the i-th type are anti-serially connected, wherein the pn-junction structure of the i-th type has an i-th junction grading coefficient m i . A first pair of the n pairs of pn-junction structures has a first junction grading coefficient m 1 and a second pair of the n pairs of pn-junction structures has a second junction grading coefficient m 2 . The junction grading coefficients m 1 , m 2 are adjusted to result in generation of a spurious third harmonic signal of the semiconductor device with a signal power level, which is at least 10 dB lower than a reference signal power level of the spurious third harmonic signal obtained for a reference case in which the first and second junction grading coefficients m 1 , m 2 are 0.25.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a first terminal and a second terminal; and   at least two pairs of anti-serially connected pn-junction structures coupled between the first and second terminals, each of the pn-junction structures having a corresponding junction grading coefficient, and the junction grading coefficients of the pn-junction structures having values selected to reduce generation of spurious odd harmonic signals across the first and second terminals.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the semiconductor device comprises one of an electrostatic discharge device or a transient voltage suppression device. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the at least two pairs of anti-serially connected pn-junction structures include a first pair and a second pair, one of the first pair and the second pair including a composite pn-junction structure having a diode structure formed on a semiconductor substrate and a voltage dependent capacitance structure laterally adjacent the pn-junction structure on the semiconductor substrate. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the composite pn-junction structure has a grading coefficient 0.5 and a breakdown voltage less than 12 volts to function as a transient voltage suppressor of signals across the first and second terminals. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the first to n junction grading coefficients m 1  to m n  satisfy within a tolerance range of ±0.05 the following ellipse equation: 
       
         
           
             
               
                 
                   
                     
                       ∑ 
                         
                     
                     
                       i 
                       = 
                       1 
                     
                     n 
                   
                   ⁢ 
                   
                     
                       ( 
                       
                         
                           
                             m 
                             i 
                           
                           - 
                           
                             0 
                             
                               , 
                               TagBox[",", "NumberComma", Rule[SyntaxForm, "0"]] 
                             
                             25 
                           
                         
                         
                           a 
                           i 
                         
                       
                       ) 
                     
                     2 
                   
                 
                 = 
                 1 
               
               , 
               
                 
                   with 
                   ⁢ 
                       
                   
                     
                       ∑ 
                         
                     
                     
                       i 
                       = 
                       1 
                     
                     n 
                   
                   ⁢ 
                   
                     
                       ( 
                       
                         1 
                         
                           a 
                           i 
                         
                       
                       ) 
                     
                     2 
                   
                 
                 = 
                 16 
               
               , 
             
           
         
         wherein the parameters a i  are determined based on a zero bias capacitance C J0i  and a junction voltage potential V Ji  of the pn-junction structure of the i-th type. 
       
     
     
         6 . The semiconductor device of  claim 1 , wherein the pn-junction structure of the at least two pairs of anti-serially connected pn-junction structures is a diode structure with an anode region and a cathode region. 
     
     
         7 . The semiconductor device of  claim 1 , wherein the at least two pairs of anti-serially connected pn-junction structures are arranged in a stacked configuration in a semiconductor substrate. 
     
     
         8 . The semiconductor device of  claim 7 , wherein differently doped semiconductor regions of the pn-junction structures extend vertically with respect to a main surface region of the semiconductor substrate into the semiconductor substrate, and a planar metallurgical pn-junction extends in parallel to a main surface region of the semiconductor substrate. 
     
     
         9 . The semiconductor device of  claim 8 , wherein one of pn-junction structures of a first pair of the at least two pairs of anti-serially connected pn-junction structures is arranged in a stacked configuration in the semiconductor substrate. 
     
     
         10 . The semiconductor device of  claim 9 , wherein the stacked configuration comprises an npn-structure with a floating base region in the semiconductor substrate. 
     
     
         11 . A semiconductor device comprising:
 a first terminal and a second terminal; and   at least two pairs of anti-serially connected pn-junction structures coupled between the first and second terminals, each of the pn-junction structures having a corresponding junction grading coefficient, and a first pair and a second pair of the at least two pairs of anti-serially connected pn-junctions structures have junction grading coefficients m 1  and m 2 , respectively, where the junction grading coefficients m 1  and m 2  have values configured to reduce a signal power level of a spurious third harmonic signal across the first and second terminals.   
     
     
         12 . The semiconductor device of  claim 11 , wherein the signal power level of the spurious third harmonic signal is at least 10 dB lower than a reference signal power level of the spurious third harmonic signal obtained for a reference case in which the first and second junction grading coefficients are equal. 
     
     
         13 . The semiconductor device of  claim 11 , wherein the semiconductor device comprises one of an electrostatic discharge device or a transient voltage suppression device. 
     
     
         14 . The semiconductor device of  claim 11 , wherein the pn-junction structure of the at least two pairs of anti-serially connected pn-junction structures is a diode structure with an anode region and a cathode region. 
     
     
         15 . A semiconductor device comprising:
 n pairs of pn-junction structures, where n is an integer ≥2, the i-th pair of the n pairs including two pn-junction structures of the i-th type that are anti-serially connected and the pn-junction structure of the i-th type having an i-th junction grading coefficient m i ; and   at least one pair of the n pairs of pn-junction structures arranged as a pair of two composite pn-junction structures, each composite pn-junction structure having a first partial pn-junction structure and a second partial pn-junction structure, the first partial pn-junction structure having a first partial junction grading coefficient m i1 , and the second partial pn-junction structure having a second partial junction grading coefficient m i2  different than the first partial junction grading coefficient m i1 , and the junction grading coefficient m i  of the composite pn-junction structure being based on a combination of the first and second partial junction grading coefficients m i1 , m i2 .   
     
     
         16 . The semiconductor device of  claim 15 , wherein each composite pn-junction structure comprises a pn-junction structure corresponding to the first partial pn-junction structure and a voltage dependent capacitance corresponding to the second partial pn-junction structure. 
     
     
         17 . The semiconductor device of  claim 16 , wherein the first and second partial grading coefficients m i1  and m i2  have values determined by doping profiles of respective regions defining the pn-junction structure and the voltage dependent capacitance and relative areas of the respective regions defining the pn-junction structure and the voltage dependent capacitance. 
     
     
         18 . The semiconductor device of  claim 15 , wherein the voltage dependent capacitance comprises an oxide region adjoining a semiconductor region, and wherein the voltage dependent capacitance includes an inversion layer formed in the semiconductor region along vertical sidewalls of a deep isolation trench structure adjoining the semiconductor region. 
     
     
         19 . The semiconductor device of  claim 15 , wherein the first and second partial pn-junction structures of a first type pn-junction structure and the first and second partial pn-junction structure of a second type pn-junction structure are arranged together in a laterally isolated common region of a semiconductor substrate. 
     
     
         20 . The semiconductor device of  claim 15 , wherein the first partial pn-junction structure is arranged to have a first partial junction grading coefficient m i1 >0.50, and wherein the second partial pn-junction structure is arranged to have a second partial junction grading coefficient m i2  between 0.30 and 0.5.