HDMI Signal Communication Over An Optical Link
Abstract
Systems and methods for HDMI signal communication over an optical communication link are described. One aspect includes receiving an HDMI control signal from an HDMI master device, and another HDMI control signal from an HDMI sink terminal via a communication resources. The method identifies half-duplex communication resource contention between the HDMI control signal and the other HDMI control signal, and transitions a communication direction of the half-duplex communication resources to give the HDMI control signal precedence over the other HDMI control signal. Subsequent to transitioning the communication direction, the method transfers the HDMI control signal to the HDMI sink terminal via the communication resources. Subsequent to transferring the HDMI control signal, the method again transitions the direction of the half-duplex communication resources, and transfers the other HDMI control signal to the HDMI master device.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A decoding and forwarding unit comprising:
an SDA interface configured to transmit or receive one or more SDA signals associated with an HDMI communication protocol; an SCL interface configured to transmit or receive one or more SCL signals associated with the HDMI communication protocol; a slave state machine configured to identify and resolve half-duplex communication resource contention between one or more transmitted SDA and SCL signals, and one or more received SDA and SCL signals; and an input/output direction control configured to switch a direction of communication of the SDA interface and the SCL interface respectively, to transition between associated receive and transmit modes, based on the resolving.
2 . The decoding and forwarding unit of claim 1 , further comprising a reconfigurable ring oscillator to provide a clock input to the slave state machine.
3 . The decoding and forwarding unit of claim 2 , wherein the ring oscillator is configurable to operate in a frequency range of 100 MHz to 400 MHz.
4 . The decoding and forwarding unit of claim 1 , wherein the slave state machine performs filtering and reshaping operations on the SDA and SCL signals.
5 . The decoding and forwarding unit of claim 1 , wherein the decoding and forwarding unit is included in an HDMI source terminal.
6 . The decoding and forwarding unit of claim 1 , wherein the decoding and forwarding unit is included in an HDMI sink terminal.
7 . The decoding and forwarding unit of claim 1 , further comprising a read request control configured to support one or more read requests associated with the HDMI communication protocol.
8 . The decoding and forwarding unit of claim 1 , further comprising a clock extension control configured to support one or more clock stretching functions associated with the HDMI communication protocol.
9 . The decoding and forwarding unit of claim 1 , wherein the slave state machine governs processing of any combination of one or more read request functions and clock stretching functions associated with the HDMI protocol.
10 . The decoding and forwarding unit of claim 1 , wherein the SDA signals and the SCL signals are time-division demultiplexed signals.
11 . A CEC decoding and forwarding unit comprising:
a CEC analyzer configured to receive a first CEC signal and a second CEC signal, wherein each of the first CEC signal and the second CEC signal is a CEC signal associated with an HDMI communication protocol; a CEC arbitrator configured to:
analyze the first CEC signal and the second CEC signal; and
resolve half-duplex communication resource contention between the first CEC signal and the second CEC signal; and
an input/output direction control configured to prioritize a transmission of the first CEC signal over a transmission of the second CEC signal.
12 . The CEC decoding and forwarding unit of claim 11 , wherein a CEC transaction direction associated with the transmission of either the first CEC signal or the second CEC signal is held unchanged till the CEC transaction is completed.
13 . The CEC decoding and forwarding unit of claim 11 , further comprising a CEC transmit and reshape unit configured to reshape either the first CEC signal or the second CEC signal, wherein the reshaping is performed only when the first CEC signal or the second CEC signal is being transmitted, respectively.
14 . The CEC decoding and forwarding unit of claim 11 , further comprising a local oscillator configured to supply a clock signal to at least one of the CEC analyzer, the CEC arbitrator, the input/output direction control, and the CEC transmit and reshape unit.
15 . The CEC decoding and forwarding unit of claim 11 , further comprising a plurality of CEC analyzers interconnected as a plurality of nodes in a CEC connection topology, wherein the CEC connection topology is configured to relay one or more CEC requests generated by one or more of the nodes, while preventing one or more CEC request deadlocks over the CEC connection topology.
16 . The CEC decoding and forwarding unit of claim 15 , wherein the deadlocks are prevented by each node performing a local CEC arbitration with each adjacent node.
17 . The CEC decoding and forwarding unit of claim 16 , wherein communication from a node that fails a local CEC arbitration is blocked from being transmitted.
18 . The CEC decoding and forwarding unit of claim 15 , wherein the CEC connection topology corresponds to an HDMI-based network.
19 . The CEC decoding and forwarding unit of claim 15 , wherein each node communicates with an adjacent node using a point-to-point communication protocol.
20 . An HDMI signal encoding scheme for generating an HDMI data packet, the generating comprising:
assembling a sequence of HDMI signals, the sequence of HDMI signals comprising ARC, SDA, ARC, SCL, ARC, CEC, ARC, and HPD signals; encoding one or more digital HDMI signals in the sequence of HDMI signals using Manchester encoding; and designating a start of the HDMI data packet by using an elongated last bit sequence from a previous HDMI data packet immediately preceding the HDMI data packet.
21 . The HDMI signal encoding scheme for generating an HDMI data packet of claim 20 , further comprising repeating the sequence of HDMI signals multiple times to construct the HDMI data packet.
22 . The HDMI signal encoding scheme for generating an HDMI data packet of claim 20 , wherein the ARC signal is an analog signal.
23 . The HDMI signal encoding scheme for generating an HDMI data packet of claim 20 , wherein inserting the ARC signal in every other data slot ensures that the ARC signal occupies a bandwidth of approximately 50% of the HDMI data packet.
24 . The HDMI signal encoding scheme for generating an HDMI data packet of claim 20 , wherein the elongated last bit sequence is used as a header for the HDMI data packet.Join the waitlist — get patent alerts
Track US2023421342A1 — get alerts on status changes and closely related new filings.
We store only your email — no account needed. See our privacy policy.