Integrated circuit pad failure detection

Abstract

An input/output (I/O) block for a semiconductor integrated circuit (IC), which includes: at least one I/O buffer, configured to define at least one signal path in respect of a connection to a remote I/O block via a communication channel, each signal path causing a respective signal edge slope; and an I/O sensor, coupled to the at least one signal path and configured to generate an output signal indicative of one or both of: (a) a timing difference between the signal edge for a first signal path and the signal edge for a second signal path, and (b) an eye pattern parameter for one or more of the at least one signal path.

What is claimed is: 
     
         1 . An input/output (I/O) block of a semiconductor integrated circuit (IC), the I/O block comprising:
 an I/O buffer coupled to a remote I/O block via a communication channel defining a signal path; and   an I/O sensor configured to generate an output signal indicative of an eye pattern parameter of the signal path.   
     
     
         2 . The I/O block of  claim 1 , wherein the least one I/O buffer comprises a transmission buffer, the at least one signal path comprising a first signal path coupled to an output of the transmission buffer that is coupled to the communication channel, the first signal path being further coupled to the remote I/O block via at least one connection bump, the output signal of the I/O sensor being further indicative of a quality of the at least one connection bump. 
     
     
         3 . The I/O block of  claim 2 , wherein the at least one signal path comprises: a third signal path coupled to the remote I/O block via a second connection bump; and a fourth signal path, the I/O sensor being coupled to the third and/or fourth signal paths and configured to generate the output signal being further indicative of one or both of: a timing difference between the signal edge for the third signal path and the signal edge for the fourth signal path, such that the output signal of the I/O sensor is indicative of a quality of the first and second connection bumps; and an eye pattern parameter for the third signal path and/or fourth signal path. 
     
     
         4 . The I/O block of  claim 2 , wherein the at least one signal path comprises a signal path that is coupled to an input of the transmission buffer and/or a signal path that is coupled to the remote I/O block via an interconnect and a connection bump between the transmission buffer and the interconnect, the output signal of the I/O sensor being further indicative of a quality of the connection bump. 
     
     
         5 . The I/O block of  claim 1 , further comprising:
 a differential buffer, configured to output a difference between a differential buffer input signal, received on a path coupled to the communication channel, and a fixed level signal, a signal path of the at least one signal path being coupled to the output of the differential buffer.   
     
     
         6 . The I/O block of  claim 5 , wherein the fixed level signal is a voltage fixed at a predetermined proportion of a DC power supply voltage for the IC, optionally wherein the predetermined proportion is dynamically adjusted and/or the predetermined proportion is 75%. 
     
     
         7 . The I/O block of  claim 1 , wherein the at least one I/O buffer comprises a reception buffer having an input that is coupled to the communication channel, a signal path of the at least one signal path being coupled to an output of the reception buffer. 
     
     
         8 . The I/O block of  claim 7 , wherein the input to the reception buffer is coupled to the remote I/O block via an interconnect and a connection bump between the interconnect and remote I/O block, the output signal of the I/O sensor being further indicative of a quality of the connection bump. 
     
     
         9 . The I/O block of  claim 1 , wherein the communication channel is configured to carry a differential signal via two signal lines, a first signal path of the at least one signal path being coupled to a first signal line and a second signal path of the at least one signal path being coupled to a second signal line. 
     
     
         10 . The I/O block of  claim 1 , wherein the I/O sensor comprises:
 a first input port coupled to a first option for a first signal path;   a second input port coupled to a second option for the first signal path;   a third input port coupled to a second signal path; and   a selector, configured to select the first or second input port in response to a received selection signal, such that the output signal of the I/O sensor is selectively indicative of a timing difference between the signal edge for the second signal path and the signal edge for the either the first option for the first signal path or the second option for the first signal path.   
     
     
         11 . The I/O block of  claim 1 , wherein the eye pattern parameter comprises one or more of: eye width; eye height; eye width jitter; and eye height fluctuation. 
     
     
         12 . The I/O block of  claim 1 , wherein the output signal comprises a pulse having a width indicative of: a timing difference between the signal edge for the first signal path and the signal edge for the second signal path; or the eye pattern parameter. 
     
     
         13 . The I/O block of  claim 1 , further comprising at least one of:
 a performance optimizer configured to adjust a parameter of the at least one I/O buffer based on the output signal of the I/O sensor; and   a repair controller configured to adjust a configuration of the I/O buffer based on the output signal of the I/O sensor.   
     
     
         14 . The I/O block of  claim 13 , wherein the repair controller is configured to, in response to the output signal of the I/O sensor, one or more of: disable a part or a whole of the IC; cause a lane remapping of at least part of the IC; and adjust a transmission buffer strength within the IC; and/or wherein the repair controller is configured to operate at an initial operation of the IC and/or during normal operation of the IC and/or wherein the adjustment is further made based on an instantaneous temperature of the IC and/or voltage of the IC. 
     
     
         15 . The I/O block of  claim 1 , further comprising:
 a time-to-digital converter, configured to receive a timing signal derived from the output signal of the I/O sensor and to provide a digital time signal based on the timing signal.