Very Low Power Microcontroller System

Abstract

A microcontroller system includes a processing unit supporting at least one near or sub Vt circuit and a plurality of memory blocks, each memory block connected to a DMA controller and independently power controlled. A power control system uses power gates to power control at least the memory blocks. In some embodiments, a wake-up interrupt controller is connected to the power control system and a voltage regulator system is used to supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system. A plurality of clocks can be connected to define clock domains associated with separate power domains.

1 . A microcontroller system comprising:
 a plurality of memory blocks each positioned in one of a plurality of power domains;   a plurality of voltage regulators, each having an output at a different voltage of a plurality of different voltages;   a plurality of power gates configured to control supply of power to the plurality of power domains from the plurality of voltage regulators;   power control logic coupled to the plurality of power gates configured to:   receive a signal from a wake-up interrupt controller; and   in response to the signal from the wake-up interrupt controller, turn on power to the plurality of power gates in a staggered sequence.   
     
     
         2 . The microcontroller system of  claim 1 , wherein further comprising one or more configuration registers, the power control logic configured to perform the staggered sequence according to data stored in the one or more configuration registers. 
     
     
         3 . The microcontroller system of  claim 1 , wherein the plurality of voltage regulators include at least one of a buck converter or a LDO. 
     
     
         4 . The microcontroller system of  claim 1 , further comprising a plurality of clocks connected to define clock domains associated with the plurality of power domains. 
     
     
         5 . The microcontroller system of  claim 4 , further comprising a direct memory access (DMA) controller coupled configured to gate the plurality of clocks with respect to the plurality of power domains. 
     
     
         6 . The microcontroller system of  claim 4 , wherein the plurality of clocks are not synchronized. 
     
     
         7 . The microcontroller system of  claim 1 , wherein the wake-up interrupt controller is configured to asynchronously respond to functional requests and select a voltage supplied to each block of the plurality of memory blocks. 
     
     
         8 . The microcontroller system of  claim 1 , wherein the wake-up interrupt controller comprises an always-on circuit. 
     
     
         9 . The microcontroller system of  claim 1 , further comprising a supply control logic coupled to the plurality of voltage regulators and configured to control voltage supplied by the plurality of voltage regulators. 
     
     
         10 . The microcontroller system of  claim 1 , further comprising level shifters positioned between the plurality of power domains and configured to transpose signals between power domains. 
     
     
         11 . An analog-to-digital converter (ADC) system comprising:
 an ADC;   a plurality of slots;   a first in first out (FIFO) buffer; and   an ADC controller configured to:
 cycle through the plurality of slots in response to triggers and store samples from the ADC in response to the triggers; 
 transfer data from the plurality of slots to the FIFO buffer; and 
 generate an interrupt when the FIFO buffer meets a threshold condition to wake up a processing unit. 
   
     
     
         12 . The ADC system of  claim 11 , wherein the ADC controller is configured to start a clock generator. 
     
     
         13 . The ADC system of  claim 11 , wherein the ADC controller is configured to scan one or more analog inputs to the ADC in response to the triggers. 
     
     
         14 . The ADC system of  claim 11 , wherein the ADC controller is configured to accumulate data in the plurality of slots prior to transferring data from the plurality of slots to the FIFO buffer. 
     
     
         15 . The ADC system of  claim 14 , wherein the ADC controller is configured with a number of samples to accumulate in each slot of the plurality of slots prior to transferring the data from each slot of the plurality of slots to the FIFO buffer. 
     
     
         16 . The ADC system of  claim 15 , ADC is configured such that the number is as high as 128. 
     
     
         17 . The ADC system of  claim 11 , wherein the ADC controller is configured to measure threshold voltages of devices coupled to the ADC system. 
     
     
         18 . The ADC system of  claim 11 , wherein the ADC controller is configured to transfer the data from each slot of the plurality of slots to the FIFO buffer by creating an entry including an identifier of each slot along with a portion of the data read from each slot. 
     
     
         19 . The ADC system of  claim 11 , wherein the ADC controller is configured with a channel selection for each slot of the plurality of slots, the channel selection identifying a channel of a plurality of analog input channels of the ADC such that a portion of the samples received from the channel will be stored by the ADC controller in the each slot. 
     
     
         20 . The ADC system of  claim 19 , wherein the ADC controller is configured with a window for a slot of the plurality of slots, the ADC controller configured to generate an interrupt in response to a sample of the samples received over the channel falling outside of the window.