Semiconductor memory device

Abstract

A semiconductor memory device includes a gate stack structure including a plurality of conductive layers stacked to be spaced apart from each other in a first direction, the gate stack structure surrounding the periphery of a polygonal opening. The semiconductor memory device also includes a stepped structure formed along a sidewall of the polygonal opening.

What is claimed is: 
     
         1 . A semiconductor memory device comprising:
 a gate stack structure including a cell array region, a first region adjacent to the cell array region, second and third regions which extend from the first region in a direction away from the cell array region and face each other, and a fourth region which faces the first region and connects the second region to the third region;   a first sub-stepped structure disposed in the first region of the gate stack structure;   a second sub-stepped structure disposed in the second region of the gate stack structure;   a third sub-stepped structure disposed in the third region of the gate stack structure; and   a fourth sub-stepped structure disposed in the fourth region of the gate stack structure,   wherein the first, second, third, and fourth sub-stepped structures are disposed at different levels in a first direction.   
     
     
         2 . The semiconductor memory device of  claim 1 , wherein the gate stack structure includes an opening surrounded by the first, second, third, and fourth regions, and
 wherein each of the first, second, third, and fourth sub-stepped structures becomes lower with closer distance to the center of the opening.   
     
     
         3 . The semiconductor memory device of  claim 1 , wherein the gate stack structure includes:
 a first stack structure including a plurality of first conductive layers stacked to be spaced apart from each other in the first direction, the plurality of first conductive layers extending to the first, second, third, and fourth regions from the cell array region;   a second stack structure including a plurality of second conductive layers stacked on the first stack structure to be spaced apart from each other in the first direction, the plurality of second conductive layers extending to the first region, the second region, and the fourth region from the cell array region;   a third stack structure including a plurality of third conductive layers stacked on the second stack structure to be spaced apart from each other in the first direction, the plurality of third conductive layers extending to the first and second regions from the cell array region; and   a fourth stack structure including a plurality of fourth conductive layers stacked on the third stack structure to be spaced apart from each other in the first direction, the fourth stack structure extending to the first region from the cell array region.   
     
     
         4 . The semiconductor memory device of  claim 3 , wherein the first sub-stepped structure is defined by an end portion of the plurality of fourth conductive layers, and becomes lower with increasing distance from the cell array region. 
     
     
         5 . The semiconductor memory device of  claim 3 , wherein the second sub-stepped structure is defined by an end portion of the plurality of third conductive layers and becomes lower with decreasing distance to the third region. 
     
     
         6 . The semiconductor memory device of  claim 3 , wherein the third sub-stepped structure is defined by an end portion of the plurality of first conductive layers and becomes lower with decreasing distance to the second region. 
     
     
         7 . The semiconductor memory device of  claim 3 , wherein the fourth sub-stepped structure is defined by an end portion of the plurality of second conductive layers and becomes lower with decreasing distance to the first region. 
     
     
         8 . The semiconductor memory device of  claim 1 , further comprising:
 a plurality of conductive gate contacts extending in the first direction from the first sub-stepped structure, the second sub-stepped structure, the third sub-stepped structure, and the fourth sub-stepped structure;   a plurality of conductive peripheral circuit contacts disposed in an opening of the gate stack structure surrounded by the first, second, third, and fourth regions; and   a plurality of conductive lines connecting the plurality of conductive gate contacts to the plurality of conductive peripheral circuit contacts.   
     
     
         9 . A semiconductor memory device comprising:
 a first stack structure including a plurality of first conductive layers stacked to be spaced apart from each other in a first direction, the plurality of first conductive layers surrounding a first opening;   a second stack structure including a plurality of second conductive layers stacked on the first stack structure to be spaced apart from each other in the first direction, the plurality of second conductive layers surrounding a second opening;   a third stack structure including a plurality of third conductive layers stacked on the second stack structure to be spaced apart from each other in the first direction, the plurality of third conductive layers surrounding a third opening; and   a fourth stack structure including a plurality of fourth conductive layers stacked on the third stack structure to be spaced apart from each other in the first direction, the plurality of fourth conductive layers surrounding a fourth opening,   wherein each of the first, second, third, and fourth openings includes a stepped sidewall, a first sidewall facing the stepped sidewall, and second and third sidewalls which are disposed between the first sidewall and the stepped sidewall and face each other, and   wherein a gradient of each of the first, second, and third sidewalls is greater than a gradient of the stepped sidewall.   
     
     
         10 . The semiconductor memory device of  claim 9 , wherein the plurality of first, second, third, and fourth conductive layers extend in a second direction and a third direction, which intersect each other from a planar viewpoint, and
 wherein the stepped sidewall includes a first stepped sidewall of the first opening, a second stepped sidewall of the second opening, a third stepped sidewall of the third opening, and a fourth stepped sidewall of the fourth opening.   
     
     
         11 . The semiconductor memory device of  claim 10 , wherein the first stepped sidewall faces in the second direction,
 the third stepped sidewall faces in a direction opposite to the second direction,   the second stepped sidewall faces in the third direction, and   the fourth stepped sidewall faces in a direction opposite to the third direction.   
     
     
         12 . The semiconductor memory device of  claim 10 , wherein the first stepped sidewall is exposed by the second, third, and fourth openings,
 the second stepped sidewall is exposed by the third and fourth openings, and   the third stepped sidewall is exposed by the fourth opening.   
     
     
         13 . The semiconductor memory device of  claim 10 , wherein the plurality of first conductive layers are disposed more distant from the center of the first opening with decreasing distance to the second stack structure,
 wherein the plurality of second conductive layers are disposed closer to the center of the second opening with decreasing distance to the first stack structure,   wherein the plurality of third conductive layers are disposed more distant from the center of the third opening with decreasing distance to the fourth stack structure, and   wherein the plurality of fourth conductive layers are disposed closer to the center of the fourth opening with decreasing distance to the third stack structure.   
     
     
         14 . The semiconductor memory device of  claim 10 , further comprising:
 a plurality of conductive gate contacts respectively connected to the plurality of first conductive layers, the plurality of second conductive layers, the plurality of third conductive layers, and the plurality of fourth conductive layers, the plurality of conductive gate contacts extending in the first direction;   a plurality of conductive peripheral circuit contacts disposed in a region in which the first, second, third, and fourth openings overlap with each other; and   a plurality of conductive lines connecting the plurality of conductive peripheral circuit contacts to the plurality of conductive gate contacts.   
     
     
         15 . A semiconductor memory device comprising:
 a gate stack structure including a plurality of conductive layers stacked to be spaced apart from each other in a first direction, the gate stack structure surrounding the periphery of a polygonal opening; and   a stepped structure formed along a sidewall of the polygonal opening,   wherein, from a planar viewpoint, the stepped structure becomes lower with decreasing distance to the center of the polygonal opening, and becomes lower clockwise or counterclockwise.   
     
     
         16 . A semiconductor memory device comprising:
 a plurality of conductive layers stacked to be spaced apart from each other in a first direction, the plurality of conductive layers connected to a memory cell array; and   a stepped structure including a plurality of end portions of the plurality of conductive layers, the stepped structure continuously extending to surround an opening,   wherein the stepped structure includes a first sub-stepped structure and a second sub-stepped structure adjacent to each other clockwise,   wherein the plurality of conductive layers include lower conductive layers stacked to be spaced apart from each other in the first direction and upper conductive layers stacked over the lower conductive layers to be spaced apart from each other in the first direction,   wherein the first sub-stepped structure includes first end portions of the upper conductive layers,   wherein the second sub-stepped structure includes second end portions of the lower conductive layers, and   wherein the first end portions and the second end portions are disposed at different levels in the first direction.   
     
     
         17 . The semiconductor memory device of  claim 16 , wherein a lowermost first end portion among the first end portions and an uppermost second portion among the second end portions are disposed at different levels in the first direction to be define a step.