System and method for electrically conductive membrane separation

Abstract

The present disclosure relates to systems and methods for electrically conductive membrane separation from a mixture solution via membrane nanofiltration, electro-filtration, or electro-extraction by: generating an electric field at the membrane filter, holding the membrane filter at a constant electric potential, or driving a constant current through the membrane filter; feeding a mixture solution through the membrane nanofiltration system; and separating a component from the mixture solution into a permeate solution.

What is claimed is: 
     
         1 . A membrane nanofiltration system for electrically conductive membrane separation comprising:
 a conductive membrane filter comprising a silicon wafer, wherein the silicon wafer comprises a first region having pores with pore sizes ranging from 1 μm to 1 mm and a second region having pores with pore sizes ranging from 1 nm to 5 μm;   an electrical contact in contact with the membrane filter, wherein electrical current can flow from the electrical contact to the conductive membrane filter; and   a counter electrode above a top surface of the membrane electrode,   wherein the membrane filter, via the electrical contact, and the counter electrode are configured to:
 generate an electric field between the membrane filter and the counter electrode; 
 hold the membrane filter at a constant electric potential; or 
 flow constant current into the membrane filter, and 
   wherein the membrane filter is configured to separate a component from a mixture solution.   
     
     
         2 . The system of  claim 1 , wherein the component of the mixture solution is selected from the group consisting of Co, Ni, Al, Mn, Fe, Li, Cu, Ag, Zn, Pt, Au, Pd, U, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Sc, Y, ions thereof, or mixtures thereof. 
     
     
         3 . The system of  claim 1 , wherein the pore size of the pores in the first region are different from the pore size of the pores in the second region. 
     
     
         4 . The system of  claim 1 , wherein the silicon wafer is monolithic silicon. 
     
     
         5 . A membrane nanofiltration system for electrically conductive membrane separation comprising:
 a conductive membrane filter comprising a silicon wafer and a dielectric, wherein the silicon wafer comprises pores with pore sizes ranging from 1 μm to 1 mm;   an electrical contact in contact with the membrane filter, wherein electrical current can flow from the electrical contact to the conductive membrane filter; and   a counter electrode above a top surface of the membrane electrode,   wherein the membrane filter, via the electrical contact, and the counter electrode are configured to:
 generate an electric field between the membrane filter and the counter electrode; 
 hold the membrane filter at a constant electric potential; or 
 flow constant current into the membrane filter, and 
   wherein the membrane filter is configured to separate a component from a mixture solution.   
     
     
         6 . The system of  claim 5 , wherein the dielectric is deposited on a surface of the silicon wafer to narrow the pores of the silicon wafer to 1 nm to 5 μm. 
     
     
         7 . The system of  claim 5 , wherein the dielectric comprises Al oxides, Si oxides, Ti oxides, Hf oxides, Sn oxides, Fe oxides, or combinations thereof. 
     
     
         8 . The system of  claim 5 , wherein the counter electrode is 0 nm to 1 μm from the conductive membrane filter. 
     
     
         9 . A method of making a conductive membrane filter, the method comprising:
 depositing a layer of silicon on a surface of a silicon wafer;   etching pores in the silicon wafer from a first surface of the silicon wafer, wherein the pores in the silicon wafer have a size ranging from 100 nm to 1 mm; and   fine etching pores in the silicon layer from a second surface of the silicon wafer, wherein the pores in the silicon wafer have a size ranging from 1 nm to 5 μm.   
     
     
         10 . The method of  claim 9 , wherein the deposited silicon layer acts as an etch stop for the etched pores from the first surface. 
     
     
         11 . The method of  claim 9 , wherein the silicon wafer is flipped 180° before each of the etching steps. 
     
     
         12 . The method of  claim 9 , wherein the pores in the silicon wafer and the silicon layer are etched using MACE. 
     
     
         13 . The method of  claim 9 , wherein the silicon layer is deposited using plasma-enhanced chemical vapor deposition. 
     
     
         14 . The method of  claim 9 , further comprising adding a protective layer of etch protectant on top of the silicon layer before etching pores in the silicon wafer. 
     
     
         15 . The method of  claim 14 , further comprising removing the protective layer after etching the pores in the silicon wafer and before fine etching pores in the silicon layer. 
     
     
         16 . A method of making a conductive membrane filter, the method comprising:
 laser-drilling pores through a silicon wafer;   depositing noble metal nanoparticles on a surface of the silicon wafer; and   chemically etching the surface of the silicon wafer to create a roughened surface.   
     
     
         17 . The method of  claim 16 , wherein the noble metal nanoparticles are also deposited on the interior surfaces of the pores. 
     
     
         18 . A method of making a conductive membrane filter, the method comprising:
 etching holes into a surface of a silicon wafer, wherein the holes do not extend the entire thickness of the membrane; and   etching pores from the opposite surface of the wafer to meet the previously etched holes, producing a selective membrane layer between the end of the holes and an opposite surface of the wafer,   wherein the pores in the selective membrane layer are smaller than the size of the holes in the silicon wafer.   
     
     
         19 . The method of  claim 18 , wherein the holes in the silicon wafer are etched using deep reactive ion etching. 
     
     
         20 . The method of  claim 18 , further comprising using an SiO 2  etching mask in the deep reactive ion etching process to control the geometry and density of the holes in the silicon wafer. 
     
     
         21 . The method of  claim 18 , wherein the pores in the selective membrane layer are etched using MACE. 
     
     
         22 . A method of making a conductive membrane filter, the method comprising:
 etching pores in a silicon wafer; and   vapor-depositing a thin layer on a surface of the silicon wafer,   wherein the thin layer narrows the pores at the surface of the silicon wafer and does not completely cover the pores, while providing a dielectric surface that allows a counter electrode to contact the silicon membrane.