Variable gain amplifier with subthreshold biasing

Abstract

This disclosure is directed to reducing output voltage distortions of Variable Gain Amplifiers (VGAs). A VGA may include a number of amplifiers each providing a portion of a total gain of the VGA. For example, a processing circuit may select one or more of the amplifiers of the VGA to provide the output signal with a selected gain. However, the selected amplifiers may provide amplified signals with one or more distortion signals when receiving a bias voltage. Systems and methods are described to reduce or cancel the distortion signals of the selected amplifiers by providing a subthreshold nonzero bias voltage (e.g., a weak voltage) to the remaining (e.g., non-selected) amplifiers of the VGA. For example, the non-selected amplifiers may receive the weak voltage to provide distortion signals with similar voltage amplitude and out of phase compared to the distortion signals of the selected amplifiers.

1 . (canceled) 
     
     
         2 . A variable gain amplifier circuit, comprising:
 a first amplifier;   a first switch coupled to the first amplifier;   a second amplifier;   a second switch coupled to the second amplifier;   a biasing circuit configured to couple to the first amplifier via the first switch and configured to couple to the second amplifier via the second switch; and   a subthreshold biasing circuit configured to couple to the first amplifier via the first switch and configured to couple to the second amplifier via the second switch, the subthreshold biasing circuit comprising a current source circuit and a first transistor coupled to the current source circuit, the first switch, and the second switch.   
     
     
         3 . The variable gain amplifier circuit of  claim 2 , wherein the variable gain amplifier circuit is configured to combine an output of the first amplifier and an output of the second amplifier. 
     
     
         4 . The variable gain amplifier circuit of  claim 2 , wherein the first amplifier is configured to generate a first amplified signal and a first distortion signal based on coupling to the biasing circuit, the second amplifier is configured to generate a first distortion cancelling signal based on coupling to the subthreshold biasing circuit, the first distortion cancelling signal reducing a power of the first distortion signal. 
     
     
         5 . The variable gain amplifier circuit of  claim 2 , wherein the second amplifier is configured to generate a second amplified signal and a second distortion signal based on coupling to the biasing circuit, the first amplifier is configured to generate a second distortion cancelling signal based on coupling to the subthreshold biasing circuit, the second distortion cancelling signal reducing a power of the second distortion signal. 
     
     
         6 . The variable gain amplifier circuit of  claim 2 , wherein the biasing circuit is configured to output a bias voltage equal to or above a bias voltage threshold, the first amplifier and the second amplifier configured to amplify an input signal based on the bias voltage. 
     
     
         7 . The variable gain amplifier circuit of  claim 2 , wherein the subthreshold biasing circuit is configured to output a first subthreshold nonzero bias voltage below a bias voltage threshold, the first amplifier and the second amplifier being configured to generate first respective distortion cancelling signals based on the first subthreshold nonzero bias voltage. 
     
     
         8 . The variable gain amplifier circuit of  claim 7 , wherein the subthreshold biasing circuit comprises a second transistor configured to couple to the first transistor via a third switch, the subthreshold biasing circuit being configured to output a second subthreshold nonzero bias voltage below the bias voltage threshold based on the second transistor coupling to the first transistor via the third switch, the first amplifier and the second amplifier being configured to generate second respective distortion cancelling signals based on the second subthreshold nonzero bias voltage. 
     
     
         9 . The variable gain amplifier circuit of  claim 8 , wherein the subthreshold biasing circuit comprises a third transistor configured to couple to the second transistor via a fourth switch, the subthreshold biasing circuit being configured to output a third subthreshold nonzero bias voltage below the bias voltage threshold based on the third transistor coupling to the first transistor and the second transistor via the third switch and the fourth switch, the first amplifier and the second amplifier being configured to generate third respective distortion cancelling signals based on the third subthreshold nonzero bias voltage. 
     
     
         10 . The variable gain amplifier circuit of  claim 2 , comprising a third amplifier, the biasing circuit configured to couple to the third amplifier via a third switch, and the first transistor coupled to the current source circuit, the first switch, the second switch, and the third switch. 
     
     
         11 . An electronic device comprising:
 an antenna;   a first amplifier;   a biasing circuit configured to couple to the first amplifier;   a subthreshold biasing circuit configured to couple to the first amplifier, the subthreshold biasing circuit comprising a current source circuit and a first transistor coupled to the current source circuit and the first amplifier; and   a processor coupled to the first amplifier, the processor being configured to couple the biasing circuit and the subthreshold biasing circuit to the first amplifier.   
     
     
         12 . The electronic device of  claim 11 , comprising a second amplifier, the processor being coupled to the second amplifier, and the processor configured to couple the biasing circuit and the subthreshold biasing circuit to the second amplifier. 
     
     
         13 . The electronic device of  claim 11 , wherein the first amplifier is configured to generate an amplified signal and a distortion signal based on coupling to the biasing circuit, and the first amplifier is configured to generate a distortion cancelling signal based on coupling to the subthreshold biasing circuit. 
     
     
         14 . The electronic device of  claim 13 , wherein the subthreshold biasing circuit is configured to output a first subthreshold nonzero bias voltage below a bias voltage threshold, the first amplifier being configured to generate a first distortion cancelling signal based on the first subthreshold nonzero bias voltage, the first distortion cancelling signal reducing a power of the distortion signal. 
     
     
         15 . The electronic device of  claim 14 , wherein the subthreshold biasing circuit comprises a second transistor configured to couple to the first transistor, the subthreshold biasing circuit being configured to output a second subthreshold nonzero bias voltage below the bias voltage threshold based on the second transistor coupling to the first transistor, the first amplifier being configured to generate a second distortion cancelling signal based on the second subthreshold nonzero bias voltage. 
     
     
         16 . The electronic device of  claim 11 , comprising:
 a transmitter comprising the first amplifier, the first amplifier configured to output amplified transmission signals to the antenna, or   a receiver comprising the first amplifier, the first amplifier configured to output amplified received signals to the processor.   
     
     
         17 . A transceiver comprising:
 a first amplifier configured to couple to an antenna;   a second amplifier configured to couple to the antenna;   a biasing circuit configured to couple to the first amplifier and the second amplifier, the biasing circuit configured to generate a bias voltage equal to or above a bias voltage threshold; and   a subthreshold biasing circuit configured to couple to the first amplifier and the second amplifier, the subthreshold biasing circuit comprising a current source circuit and a first transistor coupled to the current source circuit and configured to couple to the first amplifier and the second amplifier, the subthreshold biasing circuit configured to generate a first subthreshold nonzero bias voltage below the bias voltage threshold.   
     
     
         18 . The transceiver of  claim 17 , wherein the first amplifier is configured to generate a first amplified signal and a first distortion signal based on coupling to the biasing circuit, the second amplifier is configured to generate a first distortion cancelling signal based on coupling to the subthreshold biasing circuit, the first distortion cancelling signal reducing a power of the first distortion signal. 
     
     
         19 . The transceiver of  claim 17 , wherein the second amplifier is configured to generate a second amplified signal and a second distortion signal based on coupling to the biasing circuit, the first amplifier is configured to generate a second distortion cancelling signal based on coupling to the subthreshold biasing circuit, the second distortion cancelling signal being reducing a power of the second distortion signal. 
     
     
         20 . The transceiver of  claim 17 , wherein the subthreshold biasing circuit comprises a second transistor configured to couple to the first transistor and the current source circuit, the subthreshold biasing circuit being configured to output a second subthreshold nonzero bias voltage below the bias voltage threshold based on the second transistor coupling to the first transistor and the current source circuit, the first amplifier and the second amplifier being configured to generate second respective distortion cancelling signals based on the second subthreshold nonzero bias voltage. 
     
     
         21 . The transceiver of  claim 17 , comprising:
 a transmitter comprising the first amplifier and the second amplifier, the first amplifier and the second amplifier configured to output amplified transmission signals to the antenna; or   a receiver comprising the first amplifier and the second amplifier, the first amplifier and the second amplifier configured to output amplified received signals received by the antenna.