Smart compute resistive memory

Abstract

Systems, methods and devices are disclosed for a smart compute memory circuitry that has the flexibility to perform a wide range of functions inside the memory via logic circuitry and an integrated processor. In one embodiment, the smart compute memory circuitry comprises an integrated processor and logic circuitry to enable adaptive System on a Chip (SOC) and electronics subsystem power or performance improvements, and adaptive memory management and control for the smart compute memory circuitry. A resistive memory array is coupled to the integrated processor.

What is claimed is: 
     
         1 . A low power neuromorphic smart memory comprising:
 a plurality of intellectual property (IP) cores of the low power neuromorphic smart memory with each core including a smart compute memory circuitry; and   routing channels to interconnect the plurality of IP cores, wherein each smart compute memory circuitry includes a resistive memory array and a smart compute circuitry that functions as Intelligent Memory Management and Control to optimize parameters including memory performance and memory endurance.   
     
     
         2 . The low power neuromorphic smart memory of  claim 1 , wherein the resistive memory array comprises non-volatile random access memory (RAM) including one or more of magnetic RAM (MRAM), resistive random access memory, phase change RAM (PCRAM), ferro-electric RAM (FeRAM) or carbon nanotube memory cells. 
     
     
         3 . The low power neuromorphic smart memory of  claim 1 , wherein the smart compute memory circuitry is configured to process data with results of the processing being stored in the resistive memory array while a host system remains in a low power sleep state. 
     
     
         4 . The low power neuromorphic smart memory of  claim 1 , wherein the smart compute memory circuitry comprises a data path adder, a data path comparator, a reduction function, and control/storage registers. 
     
     
         5 . The low power neuromorphic smart memory of  claim 1 , wherein at least one IP core is configured to be trained with two dimensional (2D) data, to compute similarity or distance for data of a context or category, and to generate a closest match as an output prediction. 
     
     
         6 . The low power neuromorphic smart memory of  claim 1 , wherein the smart compute memory circuitry is configured to provide compute functions including averaging, moving average, add, subtract, compare, simple multiply/divide, minimum/maximum, and software applet functionality locally within the low power neuromorphic memory. 
     
     
         7 . The low power neuromorphic smart memory of  claim 1 , wherein the smart compute memory circuitry is configured to provide compute functions including a similarity measurement function. 
     
     
         8 . The low power neuromorphic smart memory of  claim 7 , wherein the similarity measurement function is determined based on an add/subtract function, an absolute value determination, an accumulator having an output to be compared with an input, and a register to store output for this similarity measurement. 
     
     
         9 . The low power neuromorphic smart memory of  claim 7 , wherein the smart compute memory circuitry is configured to provide compute functions including an update minimum/maximum functionality. 
     
     
         10 . The low power neuromorphic smart memory of  claim 1 , wherein each IP core is configured to receive 128 to 512 bytes of data. 
     
     
         11 . A computing system comprising:
 a central processing unit (CPU); and   a low power neuromorphic memory subsystem coupled to the CPU, the low power neuromorphic memory subsystem includes input/output (I/O) circuitry, a smart compute memory circuitry, and a resistive memory array, wherein the smart compute memory circuitry includes a smart compute circuitry that functions as Intelligent Memory Management and Control to optimize parameters including memory performance and memory endurance.   
     
     
         12 . The computing system of  claim 11 , wherein the resistive memory array comprises non-volatile random access memory (RAM) including one or more of magnetic RAM (MRAM), resistive random access memory, phase change RAM (PCRAM), ferro-electric RAM (FeRAM) or carbon nanotube memory cells. 
     
     
         13 . The computing system of  claim 11 , wherein the smart compute memory circuitry is configured to process data with results of the processing being stored in the resistive memory array while the CPU remains in a low power sleep state. 
     
     
         14 . The computing system of  claim 11 , wherein the smart compute memory circuitry comprises a data path adder, a data path comparator, a reduction function, and control/storage registers. 
     
     
         15 . The computing system of  claim 11 , wherein the smart compute memory circuitry is configured to be trained with two dimensional (2D) data, to compute similarity or distance for data of a context or category, and to generate a closest match as an output prediction. 
     
     
         16 . The computing system of  claim 11 , wherein the smart compute memory circuitry is configured to provide compute functions including averaging, moving average, add, subtract, compare, simple multiply/divide, minimum/maximum, and software applet functionality locally within the low power neuromorphic memory subsystem. 
     
     
         17 . The computing system of  claim 11 , wherein the smart compute memory circuitry is configured to provide compute functions including a similarity measurement function. 
     
     
         18 . The computing system of  claim 17 , wherein the similarity measurement function is determined based on an add/subtract function, an absolute value determination, an accumulator having an output feedback to be compared with an input, and a register to store output for this similarity measurement. 
     
     
         19 . The computing system of  claim 11 , wherein the smart compute memory circuitry is configured to provide compute functions including an update minimum/maximum functionality.