Uninterruptible power system bypass switch control

Abstract

Power systems and methods are provided that receive input power and provide output power to a load. Under a first state of operation, power conversion circuitry may receive the input power and provide the output power. A bypass switch includes a controller that detects a failure condition by detecting a link down state on a communications interface. In response to detecting the link down state, the switch controller operates the bypass switch to convey the input power to the output in a second state of operation. The second state of operation is a bypass state of operation whereby the power conversion circuitry is bypassed.

What is claimed is: 
     
         1 . A high-speed communication system for communicating one or more conditions between two or more controllers comprising:
 a first controller including a first communications interface having a first physical layer interface circuit, the first controller configured to detect a condition and, in response to detecting the condition, to generate a link reset at the first physical layer interface circuit; and   a second controller operatively coupled to the first controller and including a second communications interface having a second physical layer interface circuit, the second controller configured to detect the link reset at the second physical layer interface circuit and, in response to detecting the link reset, output a signal indicating the condition detection.   
     
     
         2 . The system of  claim 1 , wherein the second controller is further configured to confirm the link reset after a confirmation period and to take a corrective action in response to confirming the link reset. 
     
     
         3 . The system of  claim 2 , wherein the confirmation period is about 500 microseconds or less. 
     
     
         4 . The system of  claim 1  wherein the first controller includes watchdog logic configured to detect the condition by reaching a timeout threshold. 
     
     
         5 . The system of  claim 4 , wherein the timeout threshold is about 500 microseconds or less. 
     
     
         6 . The system of  claim 1  wherein the first controller includes a field programmable gate array and the first physical layer interface circuit is coupled to the field programmable gate array by a media independent interface. 
     
     
         7 . The system of  claim 1 , further comprising a bypass switch, wherein the bypass switch is controlled responsive to the signal indicating the condition detection. 
     
     
         8 . The system of  claim 2 , wherein the second controller is further configured to control a bypass switch to take the corrective action. 
     
     
         9 . A non-transitory computer-readable medium storing thereon sequences of computer-executable instructions for operating a high speed communications system having a first communications interface having a first physical layer interface circuit and including a second communications interface having a second physical layer interface circuit, wherein the first interface circuit is operatively coupled to the second interface circuit, the sequences of computer-executable instructions including instructions that instruct at least one processor to:
 detect a condition and, in response to detecting the condition, to generate a link reset at the first physical layer interface circuit; and   detect the link reset at the second physical layer interface circuit and, in response to detecting the link reset, output a signal indicating the condition detection.   
     
     
         10 . The non-transitory computer readable medium of  claim 9 , wherein the sequences of computer-executable instructions including instructions that instruct at least one processor to confirm the link reset after a confirmation period and to take a corrective action in response to confirming the link reset. 
     
     
         11 . The non-transitory computer readable medium of  claim 10 , wherein the confirmation period is about 500 microseconds or less. 
     
     
         12 . The non-transitory computer readable medium of  claim 9 , wherein the high speed communications system further includes a bypass switch, and wherein the sequences of computer-executable instructions including instructions that instruct at least one processor to control the bypass switch responsive to the signal indicating the condition detection. 
     
     
         13 . The non-transitory computer readable medium of  claim 10 , wherein the sequences of computer-executable instructions including instructions that instruct at least one processor to control a bypass switch to take the corrective action. 
     
     
         14 . A method of operating a high-speed communication system for communicating one or more conditions between two or more controllers, the high speed communications system including a first controller including a first communications interface having a first physical layer interface circuit, and a second controller operatively coupled to the first controller and including a second communications interface having a second physical layer interface circuit, the method comprising:
 detecting a condition and, in response to detecting the condition, generating a link reset at the first physical layer interface circuit; and   detecting the link reset at the second physical layer interface circuit and, in response to detecting the link reset, output a signal indicating the condition detection.   
     
     
         15 . The method of  claim 14 , further comprising confirming the link reset after a confirmation period and taking a corrective action in response to confirming the link reset. 
     
     
         16 . The method of  claim 15 , wherein the confirmation period is about 500 microseconds or less. 
     
     
         17 . The method of  claim 14  further comprising using watchdog logic to detect the condition based on the watchdog logic reaching a timeout threshold. 
     
     
         18 . The method of  claim 17 , wherein the timeout threshold is about 500 microseconds or less. 
     
     
         19 . The method of  claim 14 , wherein the high speed communications system further include a bypass switch, and the method includes controlling the bypass switch responsive to the signal indicating the condition detection. 
     
     
         20 . The method of  claim 15 , wherein taking a corrective action includes controlling a bypass switch.