Electric circuit assembly comprising a ferroelectric field effect transistor, and memory cell

Abstract

An electric circuit assembly comprising a ferroelectric field effect transistor, an electric energy source, and a resistive element having a minimum electric resistance of 100 kOhm. The resistive element is electrically connected to a drain terminal of the ferroelectric field effect transistor, and the electric energy source is electrically connected to a gate terminal and a source terminal of the ferroelectric field effect transistor.

1 - 13 . (canceled) 
     
     
         14 . An electric circuit assembly, comprising a ferroelectric field effect transistor, an electric energy source, and a resistive element having a minimum electric resistance of 100 kOhm, wherein the resistive element is electrically connected to a drain terminal of the ferroelectric field effect transistor, and the electric energy source is electrically connected to a gate terminal and a source terminal of the ferroelectric field effect transistor. 
     
     
         15 . The electric circuit assembly according to  claim 14 , wherein the electric resistance of the resistive element is 1 MOhm to 100 MOhm. 
     
     
         16 . The electric circuit assembly according to  claim 15 , wherein the resistive element is composed of a current mirror and a current generator. 
     
     
         17 . The electric circuit assembly according to  claim 14 , wherein the at least two ferroelectric field effect transistors are arranged in series with an analog-to-digital converter. 
     
     
         18 . The electric circuit assembly according to  claim 14 , wherein a plurality of ferroelectric field effect transistors are arranged in a matrix arrangement including at least two rows and at least two columns, the gate terminals of all ferroelectric field effect transistors of a single row being electrically connected to a shared word line, all source outputs of the ferroelectric field effect transistors arranged in a single column being connected to a shared source line, and all drain terminals of the ferroelectric field effect transistors arranged in a single column being connected to a shared drain line. 
     
     
         19 . The electric circuit assembly according to  claim 18 , wherein that all drain lines of each column are connected to a dedicated analog-to-digital converter, and all source lines of each column are connected to the respective resistive element. 
     
     
         20 . A memory cell, comprising an electric circuit assembly according to  claim 14 , in which the ferroelectric field effect transistor is replaced by a flash transistor. 
     
     
         21 . The memory cell according to  claim 20 , having an on/off ratio of greater than 102. 
     
     
         22 . The electric circuit assembly according to  claim 14 , wherein that, for forming a multi-bit content-addressable memory, a positively programmed ferroelectric field effect transistor and a negatively programmed ferroelectric field effect transistor are interconnected. 
     
     
         23 . A method for programming an electric circuit assembly comprising a ferroelectric field effect transistor, an electric energy source, and a resistive element having a minimum electric resistance of 100 kOhm, the resistive element being electrically connected to a drain terminal of the ferroelectric field effect transistor, and the electric energy source being electrically connected to the gate terminal and a source terminal of the ferroelectric field effect transistor, wherein the ferroelectric field effect transistor is transferred into a state of logic one or logic zero by applying an electric voltage of a defined level to one of the terminals of the ferroelectric field effect transistor and connecting the further terminals to electric zero potential. 
     
     
         24 . The method according to  claim 23 , wherein that, when a plurality of ferroelectric field effect transistors are arranged in a matrix arrangement, only the ferroelectric field effect transistor to be programmed is supplied with the electric voltage of a defined level. 
     
     
         25 . The method according to  claim 23 , wherein that, for programming, an electric voltage of +/−4 V is applied to a single ferroelectric field effect transistor, the source line and the drain line of the same row being supplied with a low voltage, preferably with a voltage of +/−2.7 V, and the word line of the same column being supplied with a lower voltage, preferably +/−1.3 V. 
     
     
         26 . The method according to  claim 23 , wherein that VT states of the ferroelectric field effect transistor are measured with the aid of an analog-to-digital converter and adapted by means of a further adaptation step using a further programming step.