US2024079850A1PendingUtilityA1

Semiconductor device and manufacturing method thereof

Assignee: HON HAI PREC IND CO LTDPriority: Sep 7, 2022Filed: Dec 28, 2022Published: Mar 7, 2024
Est. expirySep 7, 2042(~16.1 yrs left)· nominal 20-yr term from priority
H01S 5/187H01S 5/0282H01S 5/04257H01S 5/11H01S 5/0421H01S 5/04256
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Claims

Abstract

A semiconductor device includes a first contact layer, a second contact layer, an active layer, a photonic crystal layer, a passivation layer, a first electrode and a second electrode. The first contact layer has a first surface and a second surface opposite to each other. Microstructures are located on the second surface. The second contact layer is located below the first surface. The active layer is located between the first contact layer and the second contact layer. The photonic crystal layer is located between the active layer and the second contact layer. The passivation layer is located on the second contact layer. The first electrode is located on the passivation layer and is electrically connected the first surface of the first contact layer. The second electrode is located on the passivation layer and is electrically connected to the second contact layer.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a first contact layer having a first surface and a second surface opposite to the first surface, wherein the second surface has a plurality of microstructures;   a second contact layer located below the first surface of the first contact layer;   an active layer located between the first contact layer and the second contact layer;   a photonic crystal layer located between the active layer and the second contact layer;   a passivation layer located on the second contact layer;   a first electrode located on the passivation layer and electrically connected to the first surface of the first contact layer; and   a second electrode located on the passivation layer and electrically connected to the second contact layer.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the first contact layer is one of an n-type contact layer and a p-type contact layer, and the second contact layer is the other one of the n-type contact layer and the p-type contact layer. 
     
     
         3 . The semiconductor device of  claim 1 , further comprising:
 a first cladding layer located between the first contact layer and the active layer; and   a second cladding layer located between the second contact layer and the photonic crystal layer.   
     
     
         4 . The semiconductor device of  claim 3 , wherein the first contact layer, the first cladding layer, the active layer, the photonic crystal layer, the second cladding layer and the second contact layer are made of homogeneous materials. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the second electrode is in contact with the second contact layer, and a width of the second electrode in contact with the second contact layer is less than a width of the photonic crystal layer. 
     
     
         6 . The semiconductor device of  claim 1 , wherein each of the microstructures has a bottom and a protruding portion, wherein the protruding portions are disposed on the bottoms, and a projected area of the protruding portions on the bottoms is less than a projected area of the bottoms. 
     
     
         7 . The semiconductor device of  claim 6 , wherein the bottoms are square or hexagonal, and the protruding portions are circle, square, rectangular, or a combination thereof. 
     
     
         8 . A manufacturing method of a semiconductor device, comprising:
 sequentially forming a first cladding layer, a first guiding layer, an active layer, a second guiding layer, a photonic crystal layer, a second cladding layer and a second contact layer on a first surface of a first contact layer;   forming a trench in the first cladding layer, the first guiding layer, the active layer, the second guiding layer, the photonic crystal layer, the second cladding layer and the second contact layer;   forming a passivation layer in the trench and on the second contact layer, wherein the passivation layer has a first opening and a second opening, the first contact layer is exposed from the first opening, and the second contact layer is exposed from the second opening;   forming a first electrode in the first opening and on the passivation layer such that the first electrode is electrically connected to the first contact layer in the first opening;   forming a second electrode in the second opening and on the passivation layer such that the second electrode is electrically connected to the second contact layer in the second opening; and   forming a plurality of microstructures on a second surface opposite to the first surface of the first contact layer.   
     
     
         9 . The method of  claim 8 , wherein forming the microstructures on the second surface further comprises:
 disposing a hard mask layer on the second surface of the first contact layer;   forming an electron blocking layer on the hard mask layer, wherein the electron blocking layer has a plurality of patterns;   etching the hard mask layer and the first contact layer according to the patterns of the electron blocking layer to form the microstructures; and   removing the hard mask layer and the electron blocking layer.   
     
     
         10 . The method of  claim 8 , further comprising:
 coating a protective layer on the passivation layer, the first electrode and the second electrode after forming the second electrode;   planarizing the protective layer; and   etching the protective layer on the first electrode and the second electrode such that the first electrode and the second electrode are exposed from the protective layer.   
     
     
         11 . The method of  claim 8 , wherein forming the second electrode in the second opening and on the passivation layer further comprises:
 forming a photoresist layer on the first electrode and the passivation layer, wherein the second opening of the passivation layer is exposed from the photoresist layer;   forming a metal layer in the second opening and on the photoresist layer;   patterning the metal layer to form the second electrode; and   removing the photoresist layer.   
     
     
         12 . The method of  claim 11 , wherein forming the metal layer in the second opening and on the photoresist layer is performed such that a width of the metal layer in the second opening is less than a width of the photonic crystal layer. 
     
     
         13 . A semiconductor device, comprising:
 a first contact layer having a first surface and a second surface opposite to the first surface, wherein the second surface has a plurality of microstructures;   a second contact layer located below the first surface of the first contact layer;   a first guiding layer located between the first contact layer and the second contact layer;   a second guiding layer located between the first guiding layer and the second contact layer;   a photonic crystal layer located between the second guiding layer and the second contact layer;   a passivation layer located on the second contact layer;   a first electrode located on the passivation layer and electrically connected to the first surface of the first contact layer; and   a second electrode located on the passivation layer and electrically connected to the second contact layer.   
     
     
         14 . The semiconductor device of  claim 13 , wherein the first contact layer is one of an n-type contact layer and a p-type contact layer, and the second contact layer is the other one of the n-type contact layer and the p-type contact layer. 
     
     
         15 . The semiconductor device of  claim 13 , further comprising:
 a first cladding layer located between the first contact layer and the first guiding layer.   
     
     
         16 . The semiconductor device of  claim 15 , further comprising:
 a second cladding layer located between the first cladding layer and the second contact layer.   
     
     
         17 . The semiconductor device of  claim 16 , wherein the first contact layer, the first cladding layer, the first guiding layer, the second guiding layer, the photonic crystal layer, the second cladding layer and the second contact layer are made of homogeneous materials. 
     
     
         18 . The semiconductor device of  claim 13 , wherein the second electrode is in contact with the second contact layer, and a width of the second electrode in contact with the second contact layer is less than a width of the photonic crystal layer. 
     
     
         19 . The semiconductor device of  claim 13 , wherein each of the microstructures has a bottom and a protruding portion, wherein the protruding portions are disposed on the bottoms, and a projected area of the protruding portions on the bottoms is less than a projected area of the bottoms. 
     
     
         20 . The semiconductor device of  claim 19 , wherein the bottoms are square or hexagonal, and the protruding portions are circle, square, rectangular, or a combination thereof.

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