Ald vs pvd igzo channel and alox channel passivation in a 3d nand vertical wordline driver

Abstract

ALD versus PVD IGZO Channel and AlOx channel passivation in a vertical wordline driver. A pillar is formed in a stacked layer semiconductor structure including a source layer, wherein forming the pillar exposes layers in the semiconductor structure and exposes a portion of the source layer at the bottom of the pillar. A gate oxide film is formed over exposed layers in the semiconductor structure and over the exposed portion of the source layer. A sacrificial silicon liner is formed over the gate oxide, and subsequently both the gate oxide and the sacrificial silicon liner are removed from the pillar bottom in an anisotropic dry etch (“punch”) process that exposes the source layer. The sacrificial silicon liner is stripped from the gate oxide wall, and a film of IGZO is formed over the gate oxide film and a portion of the source layer, and a high-κ channel passivation deposition process follows to form a film of a high-κ material over the film of IGZO to form a hermetically sealed IGZO channel contained within a vertical wordline driver supporting a drive voltage of at least 10 volts.

What is claimed is: 
     
         1 . A method for forming a hermetically sealed Indium Gallium Zinc Oxide (IGZO) channel contained within a vertical wordline driver supporting a drive voltage of at least 10 volts comprising:
 forming a pillar having a sidewall in a stacked layer semiconductor structure including a source layer, wherein forming the pillar exposes layers in the semiconductor structure and exposes a portion of the source layer at a bottom of the pillar;   forming a gate oxide film over exposed layers in the semiconductor structure including the sidewall of the pillar and over the exposed portion of the source layer;   depositing a sacrificial silicon liner over the gate oxide;   selectively removing the sacrificial silicon liner and the gate oxide at the bottom of the pillar to punch through to the source layer; removing the sacrificial silicon liner from the gate oxide pillar sidewall;   forming a film of IGZO over the gate oxide pillar sidewall and a portion of the source layer where the gate oxide was punched through; and   using a high-κ channel passivation deposition process to form a film of a high-κ material over the film of IGZO to form a hermetically sealed IGZO channel.   
     
     
         2 . The method of  claim 1 , wherein the high-κ material comprises aluminum oxide (AlOx). 
     
     
         3 . The method of  claim 1 , wherein the pillar has an inverted conical frustum shape with VWD CD≥WC CD or has straight sidewalls with VWD CD>WC CD or VWD CD=WC CD, where VWD is vertical wordline driver, WC is wordline contact, and CD is critical dimension. 
     
     
         4 . The method of  claim 1 , wherein the high-κ material is deposited using a physical vapor deposition (PVD) process. 
     
     
         5 . The method of  claim 4 , comprising:
 using PVD to perform an IGZO deposition process to form an IGZO film over the gate oxide film and exposed source; and   using PVD to perform an aluminum oxide (AlOx) deposition process to deposit an AlOx liner (channel passivation) over the IGZO film.   
     
     
         6 . The method of  claim 5 , wherein the AlOx deposition process comprises sputtering an Al target in a chamber with Argon (Ar) and Oxygen at a wafer temperature of ≤500° C. 
     
     
         7 . The method of  claim 1 , wherein the high-κ material is deposited using an atomic layer deposition (ALD) process. 
     
     
         8 . The method of  claim 7 , comprising:
 using ALD to perform an IGZO deposition process utilizing a combination of homoleptic Ga and Zn precursors with alkyl ligands, a heteroleptic Indium (In) precursor, and a strong oxidant to form an IGZO film over the gate oxide film and exposed source; and   using at least one ALD process to perform an aluminum oxide (AlOx) deposition process to deposit an AlOx liner (channel passivation) over the IGZO.   
     
     
         9 . The method of  claim 8 , wherein the heteroleptic In precursor utilizes alkyl and alkylamino (nitrogen-containing) ligands. 
     
     
         10 . The method of  claim 8 , wherein the AlOx formation process comprises at least one AlOx liner deposition process using ALD with a strong oxidant at a wafer temperature ≤300° C. and at least one AlOx liner anneal process using a strong oxidant at a wafer temperature ≥300° C. and ≤500° C. 
     
     
         11 . The method of  claim 8 , wherein the AlOx formation process comprises:
 a first AlOx liner deposition process using ALD with a strong oxidant at a wafer temperature ≤300° C.;   a first AlOx liner anneal process using a strong oxidant at a wafer temperature ≥300° C. and ≤500° C.;   a second AlOx liner deposition process using ALD with a strong oxidant at a wafer temperature ≤300° C.;   a second AlOx liner anneal process using a strong oxidant at a wafer temperature ≥300° C. and ≤500° C.; and   a third AlOx liner deposition process using ALD with a strong oxidant at a wafer temperature ≥300° C. and ≤500° C.   
     
     
         12 . The method of  claim 1 , wherein the vertical wordline driver supports a drive voltage of at least 30 volts. 
     
     
         13 . A vertical wordline driver comprising:
 a vertical transistor structure formed in a semiconductor substrate and comprising a gate all around (GAA) structure or a double-gate structure and including,
 an outer member or wall comprising a gate oxide; 
 an IGZO (Indium Gallium Zinc Oxide) channel, adjacent to the gate oxide; 
 a channel liner, adjacent to the IGZO channel, comprising a high-κ material and forming a hermetically sealed IGZO channel of the vertical wordline driver; and 
 a dielectric fill material, 
   wherein the vertical wordline driver supports a drive voltage of at least 10 volts.   
     
     
         14 . The vertical wordline driver of  claim 13 , wherein the vertical wordline driver supports a drive voltage of at least 30 volts. 
     
     
         15 . The vertical wordline driver of  claim 13 , wherein vertical transistor structure comprises a conical frustrum shape with VWD CD≥WC CD or has straight sidewalls with VWD CD>WC CD or VWD CD=WC CD, where VWD is vertical wordline driver, WC is wordline contact, and CD is critical dimension. 
     
     
         16 . The vertical wordline driver of  claim 13 , wherein the semiconductor substrate includes a plurality of stacked layers including a layer of polysilicon comprising a gate that is in contact with a portion of the gate oxide. 
     
     
         17 . The vertical wordline driver of  claim 13 , wherein the channel liner comprises Aluminum oxide. 
     
     
         18 . The vertical wordline driver of  claim 13 , wherein the vertical transistor structure is employed as a wordline driver in a three-dimensional (3D) NAND device. 
     
     
         19 . A three-dimensional (3D) memory device, comprising:
 a semiconductor substrate including a plurality of layers;   a plurality of wordlines formed in a 3D stack of multiple tiers;   a plurality of vertical wordline drivers, each comprising,
 a vertical transistor structure formed in a semiconductor substrate and comprising a gate all around (GAA) structure or a double-gate structure including,
 an outer member or wall comprising a gate oxide; 
 an IGZO (Indium Gallium Zinc Oxide) channel, adjacent to the gate oxide; 
 a channel liner, adjacent to the IGZO channel, comprising a high-κ material and forming a hermetically sealed IGZO channel; 
 a dielectric fill material;
 an upper contact, electrically coupled to the hermetically sealed IGZO channel; and 
 a lower contact, electrically coupled to a respective wordline, 
 
 wherein the vertical wordline driver supports a drive voltage of at least 10 volts. 
 
   
     
     
         20 . The 3D memory device of  claim 19 , wherein the 3D memory device comprises a 3D NAND memory device. 
     
     
         21 . The 3D memory device of  claim 19 , wherein the plurality of layers in the semiconductor substrate includes a polysilicon layer that is in contact with the gate oxide and is used as a gate. 
     
     
         22 . The 3D memory device of  claim 19 , wherein the vertical wordline driver supports a drive voltage of at least 30 volts. 
     
     
         23 . The 3D memory device of  claim 19 , wherein the vertical transistor structure comprises a pillar having a conical frustrum shape with VWD CD≥WC CD or has straight sidewalls with VWD CD>WC CD or VWD CD=WC CD, where VWD is vertical wordline driver, WC is wordline contact, and CD is critical dimension.