US2024155953A1PendingUtilityA1

Semiconductor device and method for fabricating the same

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Assignee: SK HYNIX INCPriority: Nov 8, 2022Filed: Jun 8, 2023Published: May 9, 2024
Est. expiryNov 8, 2042(~16.3 yrs left)· nominal 20-yr term from priority
Inventors:Cha Deok DongGuk-Cheon KimBo Kyung JungKeo Rock ChoiKenichi YoshinoKazuya SawadaNaoki AkiyamaTakuya Shimano
H10B 51/30H10B 53/30H10B 61/00H10B 63/10H10B 63/00H10N 70/011H10N 70/826H10N 50/01H10N 50/80H10N 50/10H10N 70/066H10B 63/84H10N 70/063H10N 70/841H10B 61/10
56
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Claims

Abstract

A semiconductor device may include a first pattern including any one of a selector layer or a variable resistance layer and a middle electrode layer disposed over any one of the selector layer or the variable resistance layer; and a second pattern disposed over the first pattern and including the other one of the selector layer or the variable resistance layer, wherein a width of the second pattern may be the same as or greater than a width of the first pattern.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A semiconductor device comprising:
 a first pattern including any one of a selector layer or a variable resistance layer and a middle electrode layer disposed over any one of the selector layer or the variable resistance layer; and   a second pattern disposed over the first pattern and including the other one of the selector layer or the variable resistance layer,   wherein a width of the second pattern is the same as or greater than a width of the first pattern.   
     
     
         2 . The semiconductor device of  claim 1 , further comprising:
 a first capping layer disposed on sidewalls of the first pattern; and   a second capping layer disposed on sidewalls of the second pattern.   
     
     
         3 . The semiconductor device of  claim 2 , further comprising:
 a first gap-fill layer filling spaces between the first patterns; and   a second gap-fill layer filling spaces between the second patterns.   
     
     
         4 . The semiconductor device of  claim 2 , wherein the first capping layer and the second capping layer have a single-layered structure or a multi-layered structure including an insulating material, or poly-Si, or a combination thereof. 
     
     
         5 . The semiconductor device of  claim 3 , wherein the first capping layer and the first gap-fill layer include the same material. 
     
     
         6 . The semiconductor device of  claim 1 , further comprising:
 a first interlayer capping layer filling spaces between the first patterns; and   a second interlayer capping layer filling spaces between the second patterns.   
     
     
         7 . The semiconductor device of  claim 6 , wherein the first interlayer capping layer and the second interlayer capping layer have a single-layered structure or a multi-layered structure including an insulating material, or poly-Si, or a combination thereof. 
     
     
         8 . The semiconductor device of  claim 6 , wherein the first interlayer capping layer and the second interlayer capping layer include an air space formed in a void shape. 
     
     
         9 . The semiconductor device of  claim 1 , wherein the first pattern further includes a lower electrode layer disposed under any one of the selector layer or the variable resistance layer. 
     
     
         10 . The semiconductor device of  claim 1 , wherein the second pattern further includes an upper electrode layer disposed over the other one of the selector layer or the variable resistance layer. 
     
     
         11 . The semiconductor device of  claim 1 , wherein the middle electrode layer has planarized surface morphology. 
     
     
         12 . The semiconductor device of  claim 1 , wherein the variable resistance layer includes any one of a variable resistance material, a phase change material, a ferroelectric material or a ferromagnetic material. 
     
     
         13 . A method for fabricating a semiconductor device comprising:
 forming a first material layer for forming any one of a selector layer or a variable resistance layer over a substrate;   forming a second material layer for forming a middle electrode layer over the first material layer;   etching the second material layer and the first material layer through a first patterning process using a first hard mask pattern to form a first pattern including any one of the selector layer or the variable resistance layer and the middle electrode layer;   forming a third material layer for forming the other one of the selector layer or the variable resistance layer over the first pattern; and   etching the third material layer through a second patterning process using a second hard mask pattern to form a second pattern including the other one of the selector layer or the variable resistance layer.   
     
     
         14 . The method of  claim 13 , further comprising, after the forming of the first pattern,
 performing a planarization process to expose and planarize a surface of the middle electrode layer.   
     
     
         15 . The method of  claim 13 , further comprising, after the forming of the first pattern,
 performing an etchback process and a subsequent planarization process to expose and planarize a surface of the middle electrode layer.   
     
     
         16 . The method of  claim 13 , further comprising, after the forming of the first pattern,
 forming a first capping layer disposed on sidewalls of the first pattern; and   forming a first gap-fill layer filling spaces between the first patterns.   
     
     
         17 . The method of  claim 16 , wherein the first capping layer, the first gap-fill layer and the first hard mask pattern are formed by the same material as each other. 
     
     
         18 . The method of  claim 13 , further comprising, after the forming of the first pattern,
 forming a first interlayer capping layer filling spaces between the first patterns.   
     
     
         19 . The method of  claim 18 , wherein the forming of the first interlayer capping layer is performed such that the first interlayer capping layer includes an air space in a void shape by adjusting deposition conditions. 
     
     
         20 . The method of  claim 18 , wherein the first interlayer capping layer and the first hard mask pattern are formed by the same material as each other. 
     
     
         21 . The method of  claim 13 , wherein a surface of the middle electrode layer is not exposed during the etching of the third material layer. 
     
     
         22 . The method of  claim 13 , further comprising, after the forming of the second pattern,
 forming a second capping layer disposed on sidewalls of the second pattern; and   forming a second gap-fill layer filling spaces between the second patterns.   
     
     
         23 . The method of  claim 13 , further comprising, after the forming of the second pattern,
 forming a second interlayer capping layer filling spaces between the second patterns.   
     
     
         24 . The method of  claim 23 , wherein the forming of the second interlayer capping layer is performed such that the second interlayer capping layer includes an air space in a void shape by adjusting deposition conditions. 
     
     
         25 . A method for fabricating a semiconductor device comprising:
 forming a first pattern including any one of a selector layer or a variable resistance layer and a middle electrode layer disposed over any one of the selector layer or the variable resistance layer over a substrate; and   forming a second pattern including the other one of the selector layer or the variable resistance layer over the first pattern,   wherein a width of the second pattern is the same as or greater than a width of the first pattern.   
     
     
         26 . The method according to  claim 25 , wherein the forming of the first pattern includes:
 forming a first material layer for forming any one of the selector layer or the variable resistance layer over the substrate;   forming a second material layer for forming the middle electrode layer over the first material layer;   forming a first hard mask pattern over the second material layer; and   etching the second material layer and the first material layer by using the first hard mask pattern to form a structure in which any one of the selector layer or the variable resistance layer, the middle electrode layer and the first hard mask pattern are sequentially stacked.   
     
     
         27 . The method according to  claim 25 , further comprising, after the forming of the first pattern,
 performing a planarization process to expose and planarize a surface of the middle electrode layer.   
     
     
         28 . The method according to  claim 25 , further comprising, after the forming of the first pattern,
 performing an etchback process and a subsequent planarization process to expose and planarize a surface of the middle electrode layer.   
     
     
         29 . The method according to  claim 25 , further comprising, after the forming of the first pattern,
 conformally forming a first capping layer over the first pattern; and   forming a first gap-fill layer to cover the first capping layer and fill spaces between the first patterns.   
     
     
         30 . The method according to  claim 29 , wherein the first capping layer, the first gap-fill layer and the first hard mask pattern are formed by the same material. 
     
     
         31 . The method according to  claim 25 , further comprising, after the forming of the first pattern,
 forming a first interlayer capping layer to cover the first pattern and fill spaces between the first patterns.   
     
     
         32 . The method according to  claim 31 , wherein the forming of the first interlayer capping layer is performed such that the first interlayer capping layer includes an air space in a void shape by adjusting deposition conditions. 
     
     
         33 . The method according to  claim 31 , wherein the first interlayer capping layer and the first hard mask pattern are formed by the same material. 
     
     
         34 . The method according to  claim 25 , wherein the forming of the second pattern includes,
 forming a third material layer for forming the other one of the selector layer or the variable resistance layer over the first pattern;   forming a second hard mask pattern over the third material layer; and   etching the third material layer by using the second hard mask pattern to form the other one of the selector layer or the variable resistance layer over the middle electrode layer.   
     
     
         35 . The method according to  claim 34 , wherein a surface of the middle electrode layer is not exposed during the etching of the third material layer. 
     
     
         36 . The method according to  claim 25 , further comprising, after the forming of the second pattern,
 forming a second capping layer disposed on sidewalls of the second pattern; and   forming a second gap-fill layer filling spaces between the second patterns.   
     
     
         37 . The method according to  claim 25 , further comprising, after the forming of the second pattern,
 forming a second interlayer capping layer filling spaces between the second patterns.   
     
     
         38 . The method according to  claim 37 , wherein the forming of the second interlayer capping layer is performed such that the second interlayer capping layer includes an air space in a void shape by adjusting deposition conditions.

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