Dsp based compute engine for executing matrix operations

Abstract

A method implemented by a digital signal processor (DSP) including application-specific processing engines is provided. The method includes accessing, by the application-specific processing engines a configurable microcode. The configurable microcode includes a set of instructions configured to cause the application-specific processing engines to execute a matrix-based arithmetic algorithm. The method includes executing, by the application-specific processing engines, and based on the configurable microcode, the matrix-based arithmetic algorithm. Executing the matrix-based arithmetic algorithm includes receiving, by the application-specific processing engines, one or more input matrices, performing, by the application-specific processing engines, a plurality of computations based on the one or more input matrices by iteratively executing one or more of a predetermined set of arithmetic operations until the execution of the matrix-based arithmetic algorithm is completed, and generating, by the application-specific processing engines, an output corresponding to the completed execution of the matrix-based arithmetic algorithm.

What is claimed is: 
     
         1 . A method implemented by a digital signal processor (DSP) including one or more application-specific processing engines implemented on the DSP, the method comprising:
 accessing, by the one or more application-specific processing engines, and from a memory of the DSP system, a configurable microcode, wherein the configurable microcode comprises a set of instructions configured to cause the one or more application-specific processing engines to execute a matrix-based arithmetic algorithm; and   executing, by the one or more application-specific processing engines, and based on the configurable microcode, the matrix-based arithmetic algorithm, wherein executing the matrix-based arithmetic algorithm comprises:
 receiving, by the one or more application-specific processing engines, one or more input matrices; 
 performing, by the one or more application-specific processing engines, a plurality of computations based on the one or more input matrices by iteratively executing one or more of a predetermined set of arithmetic operations until the execution of the matrix-based arithmetic algorithm is completed; and 
 generating, by the one or more application-specific processing engines, an output corresponding to the completed execution of the matrix-based arithmetic algorithm. 
   
     
     
         2 . The method of  claim 1 , wherein executing the matrix-based arithmetic algorithm comprises executing, by the one or more application-specific processing engines, and based on the configurable microcode, one or more of a Cholesky decomposition algorithm, a general matrix multiplication (GeMM) algorithm, a triangular solve matrix (TRSM) algorithm, or a triangular matrix matrix multiplication (TRMM) algorithm. 
     
     
         3 . The method of  claim 1 , wherein iteratively executing one or more of the predetermined set of arithmetic operations comprises iteratively executing one or more of a multiplication operation, a reciprocal square root operation, or a reciprocal function operation. 
     
     
         4 . The method of  claim 1 , wherein the one or more application-specific processing engines comprises an arithmetic logic unit (ALU) configured to execute the one or more of the predetermined set of arithmetic operations. 
     
     
         5 . The method of  claim 1 , wherein the configurable microcode is reconfigured, and wherein the matrix-based arithmetic algorithm comprises a first matrix-based arithmetic algorithm, the method further comprising:
 accessing, by the one or more application-specific processing engines, and from the memory of the DSP system, the reconfigured microcode; and   executing, by the one or more application-specific processing engines, and based on the reconfigured microcode, a second matrix-based arithmetic algorithm, wherein the second matrix-based arithmetic algorithm is different from the first matrix-based arithmetic algorithm.   
     
     
         6 . The method of  claim 1 , receiving the one or more input matrices comprises receiving, by the one or more application-specific processing engines, a 2×2 input matrix, a 4×4 input matrix, or an 8×8 input matrix. 
     
     
         7 . The method of  claim 1 , further comprising:
 storing the output corresponding to the completed execution of the matrix-based arithmetic algorithm to the memory of the DSP system.   
     
     
         8 . A digital signal processor (DSP) including one or more application-specific processing engines implemented on the DSP, comprising:
 a memory including instructions; and   a DSP coupled to the memory, the DSP configured to execute the instructions to:
 access, by one or more application-specific processing engines, and from the memory of the DSP system, a configurable microcode, wherein the configurable microcode comprises a set of instructions configured to cause the one or more application-specific processing engines to execute a matrix-based arithmetic algorithm; and 
 execute, by the one or more application-specific processing engines, and based on the configurable microcode, the matrix-based arithmetic algorithm, wherein executing the matrix-based arithmetic algorithm comprises:
 receiving, by the one or more application-specific processing engines, one or more input matrices; 
 performing, by the one or more application-specific processing engines, a plurality of computations based on the one or more input matrices by iteratively executing one or more of a predetermined set of arithmetic operations until the execution of the matrix-based arithmetic algorithm is completed; and 
 generating, by the one or more application-specific processing engines, an output corresponding to the completed execution of the matrix-based arithmetic algorithm. 
 
   
     
     
         9 . The DSP system of  claim 8 , wherein the instructions to execute the matrix-based arithmetic algorithm further comprise instructions to execute, by the one or more application-specific processing engines, and based on the configurable microcode, one or more of a Cholesky decomposition algorithm, a general matrix multiplication (GeMM) algorithm, a triangular solve matrix (TRSM) algorithm, or a triangular matrix matrix multiplication (TRMM) algorithm. 
     
     
         10 . The DSP system of  claim 8 , wherein the instructions to iteratively execute one or more of the predetermined set of arithmetic operations further comprise instructions to iteratively execute one or more of a multiplication operation, a reciprocal square root operation, or a reciprocal function operation. 
     
     
         11 . The DSP system of  claim 8 , wherein the one or more application-specific processing engines comprises an arithmetic logic unit (ALU) configured to execute the one or more of the predetermined set of arithmetic operations. 
     
     
         12 . The DSP system of  claim 8 , wherein the configurable microcode is reconfigured, and wherein the matrix-based arithmetic algorithm comprises a first matrix-based arithmetic algorithm, the instructions further comprising instructions to:
 access, by the one or more application-specific processing engines, and from the memory of the DSP system, the reconfigured microcode; and   execute, by the one or more application-specific processing engines, and based on the reconfigured microcode, a second matrix-based arithmetic algorithm, wherein the second matrix-based arithmetic algorithm is different from the first matrix-based arithmetic algorithm.   
     
     
         13 . The DSP system of  claim 8 , wherein the instructions to receive the one or more input matrices further comprise instructions to receive, by the one or more application-specific processing engines, a 2×2 input matrix, a 4×4 input matrix, or an 8×8 input matrix. 
     
     
         14 . The DSP system of  claim 8 , wherein the instructions further comprise instructions to:
 store the output corresponding to the completed execution of the matrix-based arithmetic algorithm to the memory of the DSP system.   
     
     
         15 . A non-transitory computer-readable medium comprising instructions that, when executed by a digital signal processor (DSP) including one or more application-specific processing engines implemented on the DSP, cause the DSP to:
 access, by the one or more application-specific processing engines, and from a memory of the DSP system, a configurable microcode, wherein the configurable microcode comprises a set of instructions configured to cause the one or more application-specific processing engines to execute a matrix-based arithmetic algorithm; and   execute, by the one or more application-specific processing engines, and based on the configurable microcode, the matrix-based arithmetic algorithm, wherein executing the matrix-based arithmetic algorithm comprises:
 receiving, by the one or more application-specific processing engines, one or more input matrices; 
 performing, by the one or more application-specific processing engines, a plurality of computations based on the one or more input matrices by iteratively executing one or more of a predetermined set of arithmetic operations until the execution of the matrix-based arithmetic algorithm is completed; and 
 generating, by the one or more application-specific processing engines, an output corresponding to the completed execution of the matrix-based arithmetic algorithm. 
   
     
     
         16 . The non-transitory computer-readable medium of  claim 15 , wherein the instructions to execute the matrix-based arithmetic algorithm further comprise instructions to execute, by the one or more application-specific processing engines, and based on the configurable microcode, one or more of a Cholesky decomposition algorithm, a general matrix multiplication (GeMM) algorithm, a triangular solve matrix (TRSM) algorithm, or a triangular matrix matrix multiplication (TRMM) algorithm. 
     
     
         17 . The non-transitory computer-readable medium of  claim 15 , wherein the instructions to iteratively execute one or more of the predetermined set of arithmetic operations further comprise instructions to iteratively execute one or more of a multiplication operation, a reciprocal square root operation, or a reciprocal function operation. 
     
     
         18 . The non-transitory computer-readable medium of  claim 15 , wherein the one or more application-specific processing engines comprises an arithmetic logic unit (ALU) configured to execute the one or more of the predetermined set of arithmetic operations. 
     
     
         19 . The non-transitory computer-readable medium of  claim 15 , wherein the configurable microcode is reconfigured, and wherein the matrix-based arithmetic algorithm comprises a first matrix-based arithmetic algorithm, the instructions further comprising instructions to:
 access, by the one or more application-specific processing engines, and from the memory of the DSP system, the reconfigured microcode; and   execute, by the one or more application-specific processing engines, and based on the reconfigured microcode, a second matrix-based arithmetic algorithm, wherein the second matrix-based arithmetic algorithm is different from the first matrix-based arithmetic algorithm.   
     
     
         20 . The non-transitory computer-readable medium of  claim 15 , wherein the instructions to receive the one or more input matrices further comprise instructions to receive, by the one or more application-specific processing engines, a 2×2 input matrix, a 4×4 input matrix, or an 8×8 input matrix.