Semiconductor device patterning methods

Abstract

Methods of patterning semiconductor devices comprising selective deposition methods are described. A blocking layer is deposited on a metal surface of a semiconductor device before deposition of a dielectric material on a dielectric surface. Methods include exposing a substrate surface including a metal surface and a dielectric surface to a heterocyclic reactant comprising a headgroup and a tailgroup in a processing chamber and selectively depositing the heterocyclic reactant on the metal surface to form a passivation layer, wherein the heterocyclic headgroup selectively reacts and binds to the metal surface.

What is claimed is: 
     
         1 . A selective deposition method, the method comprising:
 exposing a substrate surface including a metal surface and a dielectric surface to a vapor phase heterocyclic reactant comprising a heterocyclic headgroup selected from the group consisting of a furan group, a phosphinine group, a phosphinoline group, and a phosphole group, and a tailgroup in a processing chamber; and   selectively depositing the vapor phase heterocyclic reactant on the metal surface to cover the metal surface with a blocking layer, wherein the heterocyclic headgroup selectively binds to the metal surface.   
     
     
         2 . The method of  claim 1 , further comprising depositing a dielectric material on the dielectric surface not covered by the blocking layer at a dielectric deposition temperature up to 350° C. at which the vapor phase heterocyclic reactant remains bound to the metal surface and maintains stability. 
     
     
         3 . The method of  claim 2 , further comprising decomposing the blocking layer covering the metal surface at a temperature higher than the dielectric deposition temperature to form a pattern on the substrate surface. 
     
     
         4 . The method of  claim 1 , wherein the tailgroup comprises one or more of a phenyl group and a carbon chain having a length in the range of from 1 to 50 carbon atoms. 
     
     
         5 . The method of  claim 4 , wherein the tailgroup comprises a carbon chain having a length in the range of from 1 to 50 carbon atoms. 
     
     
         6 . The method of  claim 2 , wherein selectively depositing the vapor phase heterocyclic reactant on the metal surface and depositing the dielectric material on the dielectric surface not covered by the blocking layer utilize an atomic layer deposition process in the processing chamber. 
     
     
         7 . The method of  claim 1 , wherein the metal surface comprises one or more of copper, cobalt, nickel, tungsten, vanadium, ruthenium, chromium, iron, platinum, gold, silver, molybdenum, gallium, indium, indium tin oxide, fluorine doped tin oxide and Al-doped zinc oxide. 
     
     
         8 . The method of  claim 1 , wherein the dielectric surface comprises one or more of SiO x , Si x N y , Si, SiON, AlO x , Al 2 O 3 , HfO x , ZrO 2 , TiO x , TiN, Ta x O 5 , Ta 2 O 5 , Y 2 O 3 , La 2 O 3 , AlN, MgO, CaF 2 , LiF, SrO, SiC, BaO, HfSiO 4 , LaAlO 3 , Nb 2 O 5 , BaTiO 3 , SrTiO 3 , Bi 4 Ti 3 O 12 , Pb(Zr, Ti)O 3 , CaCu 3 Ti 4 O 12 , LiNbO 3 , BaTiO 3 , LiNbO 3  and KNbO 3 . 
     
     
         9 . The method of  claim 1 , wherein the density of the blocking layer is in the range of from 1×10 13  to 1×10 14  molecules per cm 2 . 
     
     
         10 . The method of  claim 1 , wherein the thickness of the blocking layer is in the range of from 5 Å to 100 Å.