Memory device using wordline calibration for matrix vector multiplication

Abstract

Systems, methods, and apparatus related to memory devices that perform multiplication using memory cells. In one approach, a memory cell array has memory cells used to perform matrix vector multiplication based on summing output currents from the memory cells. A context of the memory cell array is determined by a controller (e.g., a memory controller internal or external to a memory chip having the array). The context can include, for example, memory cell conditions related to data retention stress, quick charge loss, back-pattern effects, and/or cross-temperature variations. Based on the determined context, the controller dynamically determines adjustments to wordline and/or other memory cell bias voltages used during the multiplication.

What is claimed is: 
     
         1 . A device comprising:
 a memory cell array; and   logic circuitry configured to:
 program first memory cells of the memory cell array to store first weights; 
 determine a context of the memory cell array; 
 adjust, based on the determined context, a bias applied to at least one first access line coupled to the first memory cells; and 
 perform multiplication of the first weights by first inputs by summing output currents from the first memory cells, wherein the adjusted bias is applied to the first memory cells during the multiplication. 
   
     
     
         2 . The device of  claim 1 , wherein the logic circuitry is further configured to receive, via a host interface, the first inputs from a host. 
     
     
         3 . The device of  claim 1 , wherein the logic circuitry is further configured to provide at least one first result from the multiplication, and send, via a host interface, the first result to a host. 
     
     
         4 . The device of  claim 1 , wherein the first access line is a wordline. 
     
     
         5 . The device of  claim 1 , wherein the first access line is a bitline. 
     
     
         6 . The device of  claim 1 , wherein the memory cells are resistive random access memory (RRAM) cells, phase-change memory (PCM) cells, NOR flash memory cells, or NAND flash memory cells. 
     
     
         7 . The device of  claim 1 , wherein the context includes values of weights stored in at least a portion of the first memory cells. 
     
     
         8 . The device of  claim 1 , wherein the context includes at least one of a temperature associated with the first memory cells when being programmed, or a temperature associated with the first memory cells when performing the multiplication. 
     
     
         9 . The device of  claim 1 , wherein the memory cell array comprises at least one reference cell, and the determined context includes a condition of the reference cell. 
     
     
         10 . The device of  claim 1 , wherein the logic circuitry is further configured to perform background scans when the memory cell array is not being used in an operation for a host, and wherein the context is determined using the background scans. 
     
     
         11 . The device of  claim 1 , wherein a host is configured to keep track of a physical address for a location last programmed in the memory cell array, and the determined context includes the physical address. 
     
     
         12 . A system comprising:
 at least one sensor;   a plurality of wordlines;   sensing circuitry coupled to the wordlines and configured to measure currents associated with memory cells;   voltage drivers configured to apply voltages to the wordlines; and   at least one controller configured to determine at least one result based on accumulating output currents from the memory cells, wherein weights are multiplied by inputs corresponding to data collected by the sensor.   
     
     
         13 . The system of  claim 12 , wherein the controller is further configured to program the memory cells to target output currents, and wherein the voltages are adjusted to return the memory cells to the target output currents. 
     
     
         14 . The system of  claim 12 , wherein the output currents are accumulated for a matrix vector multiplication used to generate an inference output from a neural network. 
     
     
         15 . The system of  claim 12 , wherein the controller is further configured to adjust the voltages applied to the wordline based on a time that has elapsed since programming the memory cells. 
     
     
         16 . The system of  claim 12 , wherein:
 the memory cells are NAND flash memory cells;   the controller is further configured to maintain a constant output current for each of the memory cells during each of a plurality of multiplication operations; and   voltages applied to the wordlines are adjusted for each of the multiplication operations based on string currents measured by the sensing circuitry.   
     
     
         17 . An apparatus comprising:
 a semiconductor substrate;   a memory cell array formed above the semiconductor substrate; and   a controller formed on the semiconductor substrate and configured to:
 measure a current flowing through first memory cells connected in series; 
 adjust, based on the measured current, a bias voltage applied to the first memory cells; and 
 perform multiplication based on accumulating output currents from the first memory cells using the adjusted bias voltage. 
   
     
     
         18 . The apparatus of  claim 17 , wherein prior to performing the multiplication, the first memory cells are programmed to respective threshold voltages corresponding to values of weights for a neural network. 
     
     
         19 . The apparatus of  claim 17 , wherein the memory cell array comprises NAND flash memory cells organized in pillars extending vertically upward from the semiconductor substrate. 
     
     
         20 . The apparatus of  claim 17 , wherein:
 the memory cells are NAND flash memory cells;   the current is a string current;   a bypass voltage is applied to the first memory cells when measuring the string current; and   the bias voltage is adjusted based on a difference in magnitude of the string current from a magnitude of a target string current.