Cross-coupled power multiplexing in high voltage applications

Abstract

Multiplexing circuitry comprises first switch and second switches coupled in series between a first node to receive a first supply voltage and a second node to provide an output voltage, and third and fourth switches coupled in series between a third node to receive a second supply voltage and the second node. First circuitry is to generate a first switch control signal to operate the first switch. Second circuitry is to generate a second switch control signal to operate the third switch. A first driver circuit is to generate a third switch control signal to operate the second switch. A second driver circuit is to generate a fourth switch control signal to operate the fourth switch. In a cross-coupled arrangement, the third switch control signal is based on the second switch control signal, and the fourth switch control is based on the second switch control signal.

What is claimed is: 
     
         1 . A device comprising:
 a first switched circuit path between a first input terminal and an output terminal;   a second switched circuit path between a second input terminal and the output terminal; and   a first driver circuit and a second driver circuit which are arranged in a cross-coupled configuration with the first switched circuit path and the second switched circuit path, wherein the second driver circuit is to control the second switched circuit path based on a first control signal, and wherein the first driver circuit is to control the first switched circuit path based on a second control signal.   
     
     
         2 . The device of  claim 1 , further comprising:
 first circuitry which is coupled to receive a first selection signal, to further control the first switched circuit path with the first control signal, which is based on the first selection signal, and to provide the first control signal to the second driver circuit; and   second circuitry which is coupled to receive a second selection signal which is complementary to the first selection signal, to further control the second switched circuit path with the second control signal, which is based on the second selection signal, and to provide the second control signal to the first driver circuit.   
     
     
         3 . The device of  claim 2 , wherein:
 the first switched circuit path comprises a first switch and a second switch coupled in series with each other between a first node and a second node, the first node to receive a first supply voltage;   the second switched circuit path comprises a third switch and a fourth switch coupled in series with each other between a third node and the second node, the third node to receive a second supply voltage;   the first circuitry is to control the first switch based on the first control signal;   the second circuitry is to control the third switch based on the second control signal;   the first driver circuit is to generate a third control signal, based on the second control signal, to control the second switch; and   the second driver circuit is to generate a fourth control signal, based on the first control signal, to control the fourth switch.   
     
     
         4 . The device of  claim 3 , further comprising a processor and a memory coupled to receive power from the power multiplexer based on one of the first supply voltage or the second supply voltage. 
     
     
         5 . The device of  claim 3 , wherein:
 the first driver circuit and the second driver circuit are further coupled to receive the first selection signal and the second selection signal, respectively;   the first driver circuit is to generate the third control signal further based on the first selection signal; and   the second driver circuit is to generate the fourth control signal further based on the second selection signal.   
     
     
         6 . The device of  claim 3 , wherein the first driver circuit comprises:
 a first transistor and a second transistor coupled in series with each other between the third node and a fourth node, wherein the first transistor and second transistor are of a first conductivity type, and the first driver circuit is to provide the third control signal at the fourth node; and   a third transistor and a fourth transistor coupled in series with each other between the fourth node and a fifth node, wherein the third transistor and fourth transistor are of a second conductivity type, the fifth node is to receive a third supply voltage, wherein the third supply voltage is generated from the first supply voltage, and the first supply voltage and the second supply voltage are each greater than the third supply voltage.   
     
     
         7 . The device of  claim 6 , wherein a gate of the second switch is coupled with the fourth node to receive the third control signal, and the third control signal comprises a voltage in a range from the second supply voltage to the third supply voltage. 
     
     
         8 . The device of  claim 3 , further comprising first level shifting circuitry to generate the first selection signal based on a first enable signal, wherein:
 the first selection signal is to be in a first range from the first supply voltage to a third supply voltage, wherein the first supply voltage is to be greater than the third supply voltage;   the first enable signal is to be in a second range from a fourth supply voltage to a fifth supply voltage, wherein the fourth supply voltage is to be greater than the fifth supply voltage; and   the third supply voltage is to be greater than the fifth supply voltage.   
     
     
         9 . The device of  claim 8 , wherein the second range of voltages is greater than the first range of voltages. 
     
     
         10 . The device of  claim 3 , further comprising:
 first level shifting circuitry to generate the first selection signal based on a first enable signal;   second level shifting circuitry to generate the second selection signal based on a second enable signal, wherein the second enable signal is complementary to the first enable signal; and   an inverter to generate the second enable signal from the first enable signal.   
     
     
         11 . The device of  claim 3 , wherein the first circuitry comprises:
 first inverter circuitry to receive the first selection signal and to generate the first control signal;   first buffer circuitry to receive the first control signal and to provide the first control signal to the first switch; and   wherein the second node is to provide an output supply voltage.   
     
     
         12 . A power multiplexer comprising:
 a first switched circuit path which extends to each of a first input terminal of the power multiplexer and an output terminal of the power multiplexer;   a second switched circuit path which extends to each of a second input terminal of the power multiplexer and the output terminal;   a first driver circuit and a second driver circuit;   first circuitry to generate a first control signal based on a first selection signal, wherein the first circuitry is coupled to control the first switched circuit path based on the first control signal, and further to provide the first control signal to the second driver circuit; and   second circuitry to generate a second control signal based on a second selection signal, wherein the second circuitry is coupled to control the second switched circuit path based on the second control signal, and further to provide the second control signal to the first driver circuit;   wherein the first driver circuit is coupled to further control the first switched circuit path based on the second control signal, and wherein the second driver circuit is coupled to further control the second switched circuit path based on the first control signal.   
     
     
         13 . The power multiplexer of  claim 12 , wherein:
 the first switched circuit path comprises a first switch and a second switch coupled in series with each other between a first node and a second node, the first node to receive a first supply voltage;   the second switched circuit path comprises a third switch and a fourth switch coupled in series with each other between a third node and the second node, the third node to receive a second supply voltage;   the first circuitry is to control the first switch based on the first control signal;   the second circuitry is to control the third switch based on the second control signal;   the first driver circuit is to generate a third control signal, based on the second control signal, to control the second switch; and   the second driver circuit is to generate a fourth control signal, based on the first control signal, to control the fourth switch.   
     
     
         14 . The power multiplexer of  claim 13 , wherein:
 the first driver circuit and the second driver circuit are further coupled to receive the first selection signal and the second selection signal, respectively;   the first driver circuit is to generate the third control signal further based on the first selection signal; and   the second driver circuit is to generate the fourth control signal further based on the second selection signal.   
     
     
         15 . The power multiplexer of  claim 13 , wherein the first driver circuit comprises:
 a first transistor and a second transistor coupled in series with each other between the third node and a fourth node, wherein the first transistor and second transistor are of a first conductivity type, and the first driver circuit is to provide the third control signal at the fourth node; and   a third transistor and a fourth transistor coupled in series with each other between the fourth node and a fifth node, wherein the third transistor and fourth transistor are of a second conductivity type, the fifth node is to receive a third supply voltage, wherein the third supply voltage is generated from the first supply voltage, and the first supply voltage and the second supply voltage are each greater than the third supply voltage.   
     
     
         16 . The power multiplexer of  claim 13 , wherein the first circuitry comprises:
 first inverter circuitry to receive the first selection signal and to generate the first control signal;   first buffer circuitry to receive the first control signal and to provide the first control signal to the first switch; and   wherein the second node is to provide an output supply voltage.   
     
     
         17 . A method at a power multiplexer, the method comprising:
 receiving a first supply voltage and a second supply voltage at a first input terminal and a second input terminal, respectively, wherein a first switched circuit path is between the first input terminal and an output terminal, wherein a second switched circuit path between the second input terminal and the output terminal, and wherein a first driver circuit and a second driver circuit are arranged in a cross-coupled configuration with the first switched circuit path and the second switched circuit path;   with the second driver circuit, controlling the second switched circuit path based on a first control signal; and   with the first driver circuit, controlling the first switched circuit path based on a second control signal.   
     
     
         18 . The method of  claim 17 , further comprising:
 with first circuitry:   further controlling the first switched circuit path with the first control signal, which is based on a first selection signal; and   providing the first control signal to the second driver circuit; and with second circuitry:   further controlling the second switched circuit path with the second control signal, which is based on a second selection signal which is complementary to the first selection signal; and   providing the second control signal to the first driver circuit.   
     
     
         19 . The method of  claim 18 , wherein:
 the first switched circuit path comprises a first switch and a second switch coupled in series with each other between a first node and a second node;   the second switched circuit path comprises a third switch and a fourth switch coupled in series with each other between a third node and the second node;   the first circuitry controls the first switch based on the first control signal;   the second circuitry controls the third switch based on the second control signal;   the first driver circuit generates a third control signal, based on the second control signal, to control the second switch; and   the second driver circuit generates a fourth control signal, based on the first control signal, to control the fourth switch.   
     
     
         20 . The method of  claim 19 , wherein:
 the first driver circuit and the second driver circuit receive the first selection signal and the second selection signal, respectively;   the first driver circuit generates the third control signal further based on the first selection signal; and   the second driver circuit generates the fourth control signal further based on the second selection signal.