Automatic compilation method and framework for generating a layout of integrated memory-compute circuit

Abstract

An automatic compilation method and framework for generating a layout for an integrated memory-compute circuit design is provided. The automatic compilation method comprises: constructing a design database with at least one basic design library and a collection of referencing architecture templates; receiving a user specification associated with the integrated memory-compute circuit design; selecting a referencing architecture template from the design database and parameterizing the selected architecture template according to the received user specification to generate an architecture for the integrated memory-compute circuit design; generating a physical layout based on the generated architecture according to one or more placement-and-routing algorithms; iterating a design exploration loop on the generated layout with one or more expertise experience-based optimization schemes to obtain one or more explored physical layouts; and evaluating hardware metrics of the one or more explored physical layouts to determine an optimal physical layout.

What is claimed is: 
     
         1 . An automatic compilation method for generating a layout for an integrated memory-compute circuit design, the method comprising:
 constructing a design database with at least one basic design library and a collection of referencing architecture templates;   receiving a user specification associated with the integrated memory-compute circuit design;   selecting a referencing architecture template from the design database and parameterizing the selected architecture template according to the received user specification to generate an architecture for the integrated memory-compute circuit design;   generating a physical layout based on the generated architecture according to one or more placement-and-routing algorithms;   iterating a design exploration loop on the generated layout with one or more expertise experience-based optimization schemes to obtain one or more explored physical layouts; and   evaluating hardware metrics of the one or more explored physical layouts under one or more constraint conditions to determine an optimal physical layout.   
     
     
         2 . The automatic compilation method according to  claim 1 , wherein the basic design library includes designs of memory cells, local logic elements and peripheral circuits. 
     
     
         3 . The automatic compilation method according to  claim 2 , wherein the memory cells are volatile memory cells or non-volatile memory cells. 
     
     
         4 . The automatic compilation method according to  claim 2 , wherein the local logic elements include multiplier and/or partial-sum adder. 
     
     
         5 . The automatic compilation method according to  claim 2 , wherein the peripheral circuits include row/column driver, shift accumulator, precision fusion unit, and/or controller. 
     
     
         6 . The automatic compilation method according to  claim 1 , wherein the referencing architecture templates include architecture templates abstracted from expert experience-based or user-defined architecture designs. 
     
     
         7 . The automatic compilation method according to  claim 1 , wherein the user specification includes a computer readable code and one or more constraints on the integrated memory-compute circuit design. 
     
     
         8 . The automatic compilation method according to  claim 1 , wherein the expertise experience-based optimization schemes include one or more memory cell array partitioning schemes. 
     
     
         9 . The automatic compilation method according to  claim 8 , wherein the one or more memory cell array partitioning schemes have different subarray granularities of partitioning or different orientation of partitioning. 
     
     
         10 . The automatic compilation method according to  claim 1 , wherein the one or more constraint conditions include area-priority condition or critical path latency-priority condition. 
     
     
         11 . An automatic compilation framework for generating a layout for an integrated memory-compute circuit design, the framework comprising:
 a database constructed with at least one basic design library and a collection of referencing architecture templates;   an automatic layout generator comprising:
 an architecture generator configured to: receive a user specification associated with the integrated memory-compute circuit design; select a referencing architecture template from the design database and parameterize the selected architecture template according to the received user specification to generate an architecture for the integrated memory-compute circuit design; and 
 a placement & routing processor configured to: generate a physical layout based on the generated architecture according to one or more placement-and-routing algorithms; 
   a design explorer configured to iterate a design exploration loop on the generated layout with one or more expertise experience-based optimization schemes to obtain one or more explored physical layouts; and   a hardware performance evaluator configured to evaluate hardware metrics of the one or more explored physical layouts under one or more constraint conditions to determine an optimal physical layout.   
     
     
         12 . The automatic compilation framework according to  claim 11 , wherein the basic design library includes designs of memory cells, local logic elements and peripheral circuits. 
     
     
         13 . The automatic compilation framework according to  claim 12 , wherein the memory cells are volatile memory cells or non-volatile memory cells. 
     
     
         14 . The automatic compilation framework according to  claim 12 , wherein the local logic elements include multiplier and/or partial-sum adder. 
     
     
         15 . The automatic compilation framework according to  claim 12 , wherein the peripheral circuits include row/column driver, shift accumulator, precision fusion unit, and/or controller. 
     
     
         16 . The automatic compilation framework according to  claim 11 , wherein the referencing architecture templates include architecture templates abstracted from expert experience-based or user-defined architecture designs. 
     
     
         17 . The automatic compilation framework according to  claim 11 , wherein the user specification includes a computer readable code and one or more constraints on the integrated memory-compute circuit design. 
     
     
         18 . The automatic compilation framework according to  claim 11 , wherein the expertise experience-based optimization schemes include one or more memory cell array partitioning schemes. 
     
     
         19 . The automatic compilation framework according to  claim 18 , wherein the one or more memory cell array partitioning schemes have different subarray granularities of partitioning or different orientation of partitioning. 
     
     
         20 . The automatic compilation framework according to  claim 11 , wherein the one or more constraint conditions include area-priority condition or critical path latency-priority condition.