Internal Ramp Voltage Generator for the Soft Start of DC-DC Converter

Abstract

A ramp generator for and method of generating a voltage ramp signal with very long ramping up time on a silicon chip, wherein the method includes a control loop providing a switched-capacitor circuit for generating the voltage ramp signal.

What is claimed is: 
     
         1 . An apparatus comprising:
 a soft start voltage buffer configured to generate an output voltage equal to a soft start voltage;   an offset generator configured to generate a soft start offset voltage equal to a sum of the output voltage of the soft start voltage buffer and a predetermined voltage;   a switched-capacitor circuit configured to establish the soft start voltage through charge redistribution between two different capacitors of the switched-capacitor circuit; and   a clock generator configured to generate a plurality of control signals for controlling the switched-capacitor circuit.   
     
     
         2 . The apparatus of  claim 1 , wherein:
 the switched-capacitor circuit is configured to perform voltage modulation through the charge redistribution, and wherein the charge redistribution is controlled by the plurality of control signals generated by the clock generator.   
     
     
         3 . The apparatus of  claim 2 , wherein:
 the switched-capacitor circuit comprises a first switch, a second switch, a first capacitor and a second capacitor.   
     
     
         4 . The apparatus of  claim 3 , wherein:
 the first switch and the second switch are connected in series between an input terminal and an output terminal of the switched-capacitor circuit;   the first capacitor is connected between a common node of the first switch and the second switch, and ground; and   the second capacitor is connected between the output terminal of the switched-capacitor circuit, and ground.   
     
     
         5 . The apparatus of  claim 3 , wherein:
 a ratio of a capacitor storage of the second capacitor to a capacitor storage of the first capacitor is in a range from 2 to 100.   
     
     
         6 . The apparatus of  claim 3 , wherein:
 in a clock cycle, the soft start voltage is increased by a voltage step, and wherein the voltage step is equal to the predetermined voltage times a capacitor ratio, and wherein the capacitor ratio is equal to a capacitance value of the first capacitor divided by a sum of the capacitance value of the first capacitor and a capacitance value of the second capacitor.   
     
     
         7 . The apparatus of  claim 3 , wherein:
 during a soft start process, the first switch and the second switch are controlled by two complementary signals generated by the clock generator.   
     
     
         8 . The apparatus of  claim 7 , wherein:
 the charge redistribution is carried out through turning on and off the first switch and the second switch in a complementary manner.   
     
     
         9 . The apparatus of  claim 1 , further comprising:
 a low pass filter configured to generate a final soft start ramp voltage, wherein an input of the low pass filter is connected to an output of the switched-capacitor circuit.   
     
     
         10 . The apparatus of  claim 9 , wherein the low pass filter comprises a filter resistor and a filter capacitor, and wherein:
 the filter resistor is connected between the output of the switched-capacitor circuit and an output of the apparatus; and   the filter capacitor is connected between the output of the apparatus and ground.   
     
     
         11 . The apparatus of  claim 1 , wherein:
 the clock generator is configured to receive an input signal and generate two complementary signals based on the input signal.   
     
     
         12 . The apparatus of  claim 1 , wherein:
 the offset generator is a fixed offset generator comprising a current source and a resistor, and wherein:
 the current source and the resistor are connected in series between a bias voltage source and an output terminal of the soft start voltage buffer; and 
 a common node of the current source and the resistor is connected to an input terminal of the switched-capacitor circuit. 
   
     
     
         13 . The apparatus of  claim 12 , wherein:
 the predetermined voltage is equal to a resistance value of the resistor times a current value of a current flowing through the current source.   
     
     
         14 . The apparatus of  claim 1 , wherein the soft start voltage buffer comprises an amplifier, and wherein:
 a non-inverting input of the amplifier is connected to an output terminal of the switched-capacitor circuit; and   an inverting input of the amplifier is connected to an output of the amplifier.   
     
     
         15 . A method comprising:
 in a first phase of a clock cycle, turning on a first switch and turning off a second switch to charge a first capacitor to a voltage level equal to a sum of a sampled soft start voltage and an offset voltage; and   in a second phase of the clock cycle, turning off the first switch and turning on the second switch to charge a second capacitor through charge redistribution between the first capacitor and the second capacitor.   
     
     
         16 . The method of  claim 15 , wherein:
 the first switch, the second switch, the first capacitor and the second capacitor form a switched-capacitor circuit connected between an offset generator and a low pass filter.   
     
     
         17 . The method of  claim 16 , wherein:
 the first switch and the second switch are connected in series between an input terminal and an output terminal of the switched-capacitor circuit;   the first capacitor is connected between a common node of the first switch and the second switch, and ground; and   the second capacitor is connected between the output terminal of the switched-capacitor circuit, and ground.   
     
     
         18 . The method of  claim 16 , further comprising:
 obtaining the sampled soft start voltage at the common node of the switched-capacitor circuit and the low pass filter.   
     
     
         19 . The method of  claim 16 , further comprising:
 generating, by a soft start voltage buffer, the sampled soft start voltage; and   generating, by the offset generator, the offset voltage.   
     
     
         20 . The method of  claim 19 , wherein:
 the offset generator comprises a current source and a resistor, and wherein:
 the current source and the resistor are connected in series between a bias voltage source and an output terminal of the soft start voltage buffer; and 
 a common node of the current source and the resistor is connected to an input terminal of the switched-capacitor circuit; and 
   the soft start voltage buffer comprises an amplifier, and wherein:
 a non-inverting input of the amplifier is connected to an output terminal of the switched-capacitor circuit; and 
 an inverting input of the amplifier is connected to an output of the amplifier.