Semiconductor device including heat shield

Abstract

Techniques that separate the heat generation from the active device and that add a thermal heat shield layer between the heat generation and the active device to reduce the channel temperature in the areas that determine the reliability of a semiconductor device.

1 . A compound semiconductor heterostructure transistor device having at least one two-dimensional electron gas channel and buried heat shielding, the compound semiconductor heterostructure transistor device comprising:
 a substrate;   an electrode region having at least one gate electrode, the electrode region formed over the substrate;   a first buried two-dimensional electron gas (2DEG) channel, wherein the first buried 2DEG channel is more electrically conductive than either a first semiconductor material layer or a second semiconductor material layer formed over the first semiconductor material to form a first compound semiconductor heterostructure; and   a buried heat shield layer formed between the electrode region and the buried 2DEG channel.   
     
     
         2 . The compound semiconductor heterostructure transistor device of  claim 1 , comprising:
 a third semiconductor material layer formed over a fourth semiconductor material layer, wherein the fourth semiconductor material layer is formed over the substrate, to form a second compound semiconductor heterostructure having a topside second 2DEG channel, wherein the topside second 2DEG channel is more electrically conductive than either the third semiconductor material layer or the fourth semiconductor material layer.   
     
     
         3 . The compound semiconductor heterostructure transistor device of  claim 2 , wherein the electrode region includes:
 a drain electrode electrically coupled to the first semiconductor layer;   a source electrode electrically coupled to the topside second 2DEG channel; and   a gate electrode formed over the third semiconductor material layer.   
     
     
         4 . The compound semiconductor heterostructure transistor device of  claim 2 , wherein the heat shield layer is formed between the fourth semiconductor material layer and the second semiconductor material layer, and wherein the heat shield layer includes a fifth semiconductor material layer. 
     
     
         5 . The compound semiconductor heterostructure transistor device of  claim 1 , wherein the buried heat shield layer includes aluminum gallium nitride. 
     
     
         6 . The compound semiconductor heterostructure transistor device of  claim 5 , wherein an aluminum content of the aluminum gallium nitride is within a range of 25-80%. 
     
     
         7 . The compound semiconductor heterostructure transistor device of  claim 1 , wherein the electrode region includes a source electrode, the compound semiconductor heterostructure transistor device comprising:
 at least one heat pad coupled to the source electrode.   
     
     
         8 . The compound semiconductor heterostructure transistor device of  claim 7 , wherein the at least one heat pad includes copper. 
     
     
         9 . The compound semiconductor heterostructure transistor device of  claim 8 , wherein the copper has a thickness in range of 20-50 micrometers. 
     
     
         10 . The compound semiconductor heterostructure transistor device of  claim 1 , comprising:
 a second buried two-dimensional electron gas (2DEG) channel, wherein the second buried 2DEG channel is more electrically conductive than either a sixth semiconductor material layer or a seventh semiconductor material layer formed over the sixth semiconductor material to form a second compound semiconductor heterostructure.   
     
     
         11 . A method of forming a compound semiconductor heterostructure transistor device having buried heat shielding, the method comprising:
 forming a field plate region in or adjacent to a substrate;   forming an electrode region over the substrate, wherein the electrode region has at least one gate electrode;   forming a first buried two-dimensional electron gas (2DEG) channel, wherein the first buried 2DEG channel is more electrically conductive than either a first semiconductor material layer or a second semiconductor material layer formed over the first semiconductor material to form a first compound semiconductor heterostructure; and   forming a buried heat shield layer between the electrode region and the buried 2DEG channel.   
     
     
         12 . The method of  claim 11 , comprising:
 forming a third semiconductor material layer over a fourth semiconductor material layer, wherein the fourth semiconductor material layer is formed over the substrate, to form a second compound semiconductor heterostructure having a topside second 2DEG channel, wherein the topside second 2DEG channel is more electrically conductive than either the third semiconductor material layer or the fourth semiconductor material layer.   
     
     
         13 . The method of  claim 12 , wherein forming the electrode region over the substrate includes:
 electrically coupling a drain electrode to the first semiconductor layer;   electrically coupling a source electrode to the topside second 2DEG channel; and   forming a gate electrode over the third semiconductor material layer.   
     
     
         14 . The method of  claim 11 , wherein forming an electrode region over the substrate includes forming a source electrode, the method further comprising:
 coupling at least one heat pad to the source electrode.   
     
     
         15 . The method of  claim 14 , wherein the at least one heat pad includes copper. 
     
     
         16 . The method of  claim 15 , wherein the copper has a thickness in range of 20-50 micrometers. 
     
     
         17 . The method of  claim 11 , comprising:
 forming a second buried two-dimensional electron gas (2DEG) channel, wherein the second buried 2DEG channel is more electrically conductive than either a sixth semiconductor material layer or a seventh semiconductor material layer formed over the sixth semiconductor material to form a second compound semiconductor heterostructure.   
     
     
         18 . A semiconductor device having buried heat shielding, the semiconductor device comprising:
 a substrate;   an electrode region formed over the substrate;   a buried current carrying layer formed over the substrate; and   a buried heat shield layer formed between the electrode region and the buried current carrying layer.   
     
     
         19 . The semiconductor device of  claim 18 , wherein the buried heat shield layer includes aluminum gallium nitride. 
     
     
         20 . The semiconductor device of  claim 19 , wherein an aluminum content of the aluminum gallium nitride is within a range of 25-80%.