Semiconductor memory device

Abstract

According to one embodiment, a semiconductor memory device includes a substrate expanding in a first direction and a second direction, a plurality of conductive layers arranged in a third direction with a distance therebetween, the conductive layers including a first conductive layer, and each including a first portion and a second portion being arranged with the first portion in the second direction and including a terrace portion provided so as not to overlap an upper conductive layer in the third direction, a first insulating portion provided between the first portions and the second portions, and a first insulating layer arranged with the first portion of the first conductive layer in the second direction with the first insulating portion interposed therebetween.

1 . A semiconductor memory device comprising:
 a substrate extending in a first direction and a second direction crossing each other, the substrate including a first area, a second area, and a third area which are arranged in the first direction with the second area between the first area and the third area;   a plurality of first conductive layers separate from each other and arranged in a third direction crossing the first direction and the second direction, the first conductive layers each including a first portion and a second portion which are arranged in the second direction and are electrically connected to each other, the first portion extending in the first direction over the second area between the first area and the third area, the second portion including a terrace portion not overlapping an upper one or more of the first conductive layers in the third direction;   a plurality of contacts each connected to, and each extending in the third direction above, the terrace portion of a corresponding one of the first conductive layers;   a first member and a second member separate from each other and arranged in the first direction between first portions and second portions of the first conductive layers, the first member and the second member each including an upper end higher than an uppermost one of the first conductive layers and a lower end lower than a lowermost one of the first conductive layers, the first member overlapping a first group of the contacts in the second direction, the second member overlapping a second group of the contacts in the second direction;   a first memory pillar extending through the first conductive layers in the first area and including a portion which intersects a part of the first conductive layers and functions as a first memory cell transistor; and   a second memory pillar extending through the first conductive layers in the third area and including a portion which intersects a part of the first conductive layers and functions as a second memory cell transistor.   
     
     
         2 . The semiconductor memory device according to  claim 1 , wherein terrace portions of the first conductive layers are arranged in the first direction. 
     
     
         3 . The semiconductor memory device according to  claim 1 , further comprising:
 a plurality of second conductive layers separate from each other and arranged in the third direction, the second conductive layers each including a first portion and a second portion which are arranged in the second direction and are electrically connected to each other, the first portion extending in the first direction over the second area between the first area and the third area, the second portion including a terrace portion not overlapping an upper one or more of the second conductive layers in the third direction, wherein the first conductive layers and the second conductive layers are arranged in the second direction and electrically insulated from each other; and   a third member between the first conductive layers and the second conductive layers, the third member extending in the first direction over the second area and electrically insulating the first conductive layers and the second conductive layers from each other, the third member being located on a side opposite to the second portions of the first conductive layers with respect to the first portions of the first conductive layers in the second direction and opposite to second portions of the second conductive layers with respect to first portions of the second conductive layers in the second direction.   
     
     
         4 . The semiconductor memory device according to  claim 3 , wherein the third member extends in the first direction over the first area, the second area, and the third area between the first conductive layers and the second conductive layers. 
     
     
         5 . The semiconductor memory device according to  claim 3 , wherein the first and second members differ in structure from the third member. 
     
     
         6 . The semiconductor memory device according to  claim 1 , wherein the first portions and the second portions of the first conductive layers are coupled with each other between the first member and the second member. 
     
     
         7 . The semiconductor memory device according to  claim 1 , wherein the first member and the second member are in contact with the first portions of the first conductive layers. 
     
     
         8 . The semiconductor memory device according to  claim 1 , wherein the first group of the contacts are arranged in the first direction and the second group of the contacts are arranged in the first direction. 
     
     
         9 . The semiconductor memory device according to  claim 1 , further comprising a third conductive layer above the uppermost one of the first conductive layers,
 wherein no portions of the third conductive layer extend in the first direction in the second area between the first area and the third area.   
     
     
         10 . The semiconductor memory device according to  claim 9 , wherein
 the first memory pillar extends through the third conductive layer in the first area and includes a portion which intersects the third conductive layer and functions as a first select transistor, and   the second memory pillar extends through the third conductive layer in the third area and includes a portion which intersects the third conductive layer and functions as a second select transistor.   
     
     
         11 . A semiconductor memory device comprising:
 a substrate extending in a first direction and a second direction crossing each other, the substrate including a first area, a second area, and a third area which are arranged in the first direction with the second area between the first area and the third area;   a plurality of first conductive layers separate from each other and arranged in a third direction crossing the first direction and the second direction, the first conductive layers each including a first portion and a second portion which are arranged in the second direction and are electrically connected to each other, the first portion extending in the first direction over the second area between the first area and the third area, the second portion including a terrace portion not overlapping an upper one or more of the first conductive layers in the third direction;   a first member and a second member separate from each other and arranged in the first direction between first portions and second portions of the first conductive layers, the first member and the second member each including an upper end higher than an uppermost one of the first conductive layers and a lower end lower than a lowermost one of the first conductive layers;   a first memory pillar extending through the first conductive layers in the first area and including a portion which intersects a part of the first conductive layers and functions as a first memory cell transistor; and   a second memory pillar extending through the first conductive layers in the third area and including a portion which intersects a part of the first conductive layers and functions as a second memory cell transistor,   wherein   terrace portions of the first conductive layers are arranged in the first direction, and   the first member and the second member each have a length in the first direction that is larger than twice a length of each of the terrace portions in the first direction.   
     
     
         12 . The semiconductor memory device according to  claim 11 , wherein the first portions of the first conductive layers except the uppermost one of the first conductive layers include no terrace portions arranged in the first direction. 
     
     
         13 . The semiconductor memory device according to  claim 11 , further comprising:
 a plurality of second conductive layers separate from each other and arranged in the third direction, the second conductive layers each including a first portion and a second portion which are arranged in the second direction and are electrically connected to each other, the first portion extending in the first direction over the second area between the first area and the third area, the second portion including a terrace portion not overlapping an upper one or more of the second conductive layers in the third direction, wherein the first conductive layers and the second conductive layers are arranged in the second direction and electrically insulated from each other; and   a third member between the first conductive layers and the second conductive layers, the third member extending in the first direction over the second area and electrically insulating the first conductive layers and the second conductive layers from each other, the third member being located on a side opposite to the second portions of the first conductive layers with respect to the first portions of the first conductive layers in the second direction and opposite to second portions of the second conductive layers with respect to first portions of the second conductive layers in the second direction.   
     
     
         14 . The semiconductor memory device according to  claim 13 , wherein the third member extends in the first direction over the first area, the second area, and the third area between the first conductive layers and the second conductive layers. 
     
     
         15 . The semiconductor memory device according to  claim 13 , wherein the first and second members differ in structure from the third member. 
     
     
         16 . The semiconductor memory device according to  claim 11 , wherein the first portions and the second portions of the first conductive layers are coupled with each other between the first member and the second member. 
     
     
         17 . The semiconductor memory device according to  claim 11 , wherein the first member and the second member are in contact with the first portions of the first conductive layers. 
     
     
         18 . The semiconductor memory device according to  claim 11 , further comprising a plurality of contacts each connected to, and each extending in the third direction above, the terrace portion of a corresponding one of the first conductive layers. 
     
     
         19 . The semiconductor memory device according to  claim 11 , further comprising a third conductive layer above the uppermost one of the first conductive layers,
 wherein no portions of the third conductive layer extend in the first direction in the second area between the first area and the third area.   
     
     
         20 . The semiconductor memory device according to  claim 19 , wherein
 the first memory pillar extends through the third conductive layer in the first area and includes a portion which intersects the third conductive layer and functions as a first select transistor, and   the second memory pillar extends through the third conductive layer in the third area and includes a portion which intersects the third conductive layer and functions as a second select transistor.