Radio frequency chip, algorithm reconstruction method and computer-readable storage medium

Abstract

The present application relate to the technical field of mobile communication, and in particular to a radio frequency chip, an algorithm reconstruction method and a computer-readable storage medium. The radio frequency chip includes a configuration interface, an interconnection bus, a processor and at least two operation units. Each operation unit is provided with different operation functions. The configuration interface is connected to the processor, and is configured to transmit the received routing information and the configuration data to the processor. The routing information and the configuration data are determined according to a target operation function of the radio frequency chip. The interconnection bus is communicated with each operation unit and is connected to the processor, and is configured to adjust an input and output relationship between each operation unit.

1 . A radio frequency chip, comprising a configuration interface, an interconnection bus, a processor and at least two operation units, wherein:
 each operation unit is provided with different operation functions;   the configuration interface is connected to the processor, and the configuration interface is configured to receive routing information and configuration data and transmit the routing information and the configuration data to the processor; the routing information and the configuration data are determined according to a target operation function of the radio frequency chip;   the interconnection bus is communicated with each operation unit and is connected to the processor, and the interconnection bus is configured to adjust an input and output relationship between each operation unit according to an instruction of the processor;   the operation unit is connected to the processor, and the operation unit configures the operation function as the target operation function according to the configuration data allocated by the processor; and   the processor is configured to send an instruction for adjusting a routing connection mode of each operation unit to the interconnection bus, and send allocated configuration data to each operation unit.   
     
     
         2 . The radio frequency chip according to  claim 1 , wherein the operation unit comprises a first operation unit with arithmetic operation function and a second operation unit with lookup table operation function. 
     
     
         3 . The radio frequency chip according to  claim 2 , wherein:
 the first operation unit comprises N real number multiplication units, N real number addition units, 2N inverse through units, (N+2) configurable delay unit, and N is a positive integer;   the first operation unit comprises a first input terminal and a first output terminal, and each of the first input terminal and the first output terminal is connected to one configurable delay unit respectively;   the real number addition unit, the inverse through unit corresponding to the real number addition unit, the configurable delay unit corresponding to the real number addition unit are connected to the interconnection bus in sequence; and   the real number multiplication unit, the inverse through unit corresponding to the real number multiplication unit are connected to the interconnection bus in sequence.   
     
     
         4 . The radio frequency chip according to  claim 3 , wherein:
 the first operation unit comprises 4N real number multiplication units, 4N real number addition units, 8N inverse through units, (4N+2) configurable delay unit, and N is a positive integer;   the first operation unit comprises the first input terminal and the first output terminal, and each of the first input terminal and the first output terminal is connected to one configurable delay unit respectively;   the real number addition unit, the inverse through unit corresponding to the real number addition unit, the configurable delay unit corresponding to the real number addition unit are connected to the interconnection bus in sequence; and   the real number multiplication unit, the inverse through unit corresponding to the real number multiplication unit are connected to the interconnection bus in sequence.   
     
     
         5 . The radio frequency chip according to  claim 2 , wherein:
 the second operation unit comprises 3M configurable delay units, M complex multiplication units, M complex addition units, M configurable address generation units, M lookup tables, and a multiplex selection unit, and M is a positive integer;   the configurable address generation unit comprises a second input terminal and a second output terminal; the second input terminal is connected to the configuration interface through a corresponding configurable delay unit, and the second output terminal is connected to an input terminal of the lookup table corresponding to the configurable address generation unit;   an output terminal of the lookup table is respectively connected to the complex multiplication unit corresponding to the lookup table, the complex addition unit, and an input terminal of the multiplex selection unit;   another input terminal of the complex multiplication unit is connected to the configurable delay unit corresponding to the complex multiplication unit, and an output terminal of the complex multiplication unit is connected to the input terminal of the multiplex selection unit;   another input terminal of the complex addition unit is connected to the configurable delay unit corresponding to the complex addition unit, and an output terminal of the complex addition unit is connected to the input terminal of the multiplex selection unit; and   an output terminal of the multiplex selection unit is respectively connected to the configurable delay unit corresponding to the multiplex selection unit, and the interconnection bus in sequence.   
     
     
         6 . The radio frequency chip according to  claim 1 , wherein:
 the interconnection bus is further communicated with each internal unit of each operation unit, and the interconnection bus is further configured to adjust the input and output relationship between each internal unit of each operation unit according to the instruction of the processor; and   the processor is further configured to send an instruction for adjusting the routing connection mode of each internal unit of each operation unit to the interconnection bus.   
     
     
         7 . An algorithm reconstruction method, applied to a radio frequency chip, wherein:
 the radio frequency chip comprises at least two operation units, and each operation unit is provided with different operation functions;   the method comprises:   obtaining routing information and configuration data through a configuration interface; wherein the routing information and the configuration data are determined according to a target operation function of the radio frequency chip; and   adjusting, by an interconnection bus, an input and output relationship between each operation unit according to the routing information, and sending allocated configuration data to each operation unit according to the configuration data for each operation unit to configure the operation function as the target operation function according to received configuration data.   
     
     
         8 . The algorithm reconstruction method according to  claim 7 , wherein the operation unit comprises a first operation unit and a second operation unit;
 the sending the allocated configuration data to each operation unit according to the configuration data comprises:   sending allocated first configuration data to the first operation unit for the first operation unit to configure the operation function as a target arithmetic operation function; and/or   sending the allocated second configuration data to the second operation unit for the second operation unit to configure the operation function as a target lookup table operation function.   
     
     
         9 . The algorithm reconstruction method according to  claim 1 , further comprising:
 adjusting, by the interconnection bus, the input and output relationship between each internal unit of each operation unit.   
     
     
         10 . A computer-readable storage medium, storing a computer program, wherein when the computer program is executed by a processor, the algorithm reconstruction method according to  claim 1  is implemented.