Interface circuit for converting a serial data stream to a parallel data scheme with data strobe preamble information in the serial data stream

Abstract

Technologies for converting serial data stream to a parallel data and strobe scheme with data strobe preamble information in the serial data stream are described. A device includes an interface circuit that receives a serial data stream and converts the serial data stream to parallel data and a data strobe (DQS) signal associated with the parallel data using N-bit header fields inserted into the serial data stream. The N-bit header fields specify DQS preamble information for the parallel data.

1 . (canceled) 
     
     
         2 . A data buffer device comprising:
 a first serial interface;   a first parallel interface; and   an interface circuit coupled between the first serial interface and the first parallel interface, wherein the interface circuit is to:
 receive a serial data stream from the first serial interface, the serial data stream comprising header fields inserted into the serial data stream, wherein the header fields specify data strobe (DQS) preamble information; 
 convert the serial data stream to parallel data and a DQS signal associated with the parallel data using the header fields; and 
 output the parallel data and the DQS signal on the first parallel interface. 
   
     
     
         3 . The data buffer device of  claim 2 , further comprising:
 a second serial interface, wherein the first serial interface is a first host serial interface between a host device and the data buffer device, wherein the second serial interface is a second host serial interface between the host device and the data buffer device; and   a second parallel interface, wherein the first parallel interface is a first memory device parallel interface between a memory device and the data buffer device, wherein the second parallel interface is a second memory device parallel interface between the memory device and the data buffer device.   
     
     
         4 . The data buffer device of  claim 2 , wherein the interface circuit is a serializer-deserializer (SerDes) circuit. 
     
     
         5 . The data buffer device of  claim 2 , wherein the interface circuit comprises:
 a deserializer circuit to receive the serial data stream and to convert the serial data stream into packets, wherein the packets comprise at least the parallel data and a preamble packet;   a latch coupled to an output of the deserializer circuit to store the packets;   a packet decoder coupled to the latch, the packet decoder to decode the packets and output the parallel data and the DQS signal;   a set of line drivers coupled to the packet decoder, the set of line drivers to drive data signals corresponding to the parallel data on a set of data lines of the first parallel interface; and   a strobe driver coupled to the packet decoder, the strobe driver to drive the DQS signal on a strobe line of the first parallel interface.   
     
     
         6 . The data buffer device of  claim 5 , wherein the deserializer circuit comprises:
 a first buffer to store a first portion of the packets according to a boundary indicator; and   a second buffer to store a second portion of the packets according to the boundary indicator, wherein the first portion and the second portion are barrel shifted out of the first buffer and the second buffer as an N-bit packet, where N is an integer greater than one.   
     
     
         7 . The data buffer device of  claim 5 , wherein the deserializer circuit is a 1: N deserializer, where N is an integer greater than one. 
     
     
         8 . The data buffer device of  claim 5 , wherein the packet decoder comprises a finite state machine (FSM). 
     
     
         9 . The data buffer device of  claim 2 , wherein the interface circuit comprises:
 a deserializer circuit to receive the serial data stream and to convert the serial data stream into packets, wherein the packets comprise at least the parallel data;   a set of latches coupled to an output of the deserializer circuit to store the packets over multiple clock cycles;   a multiplexer coupled to outputs of some of the set of latches;   a packet decoder coupled to an output of a first latch in the set of latches and an output of the multiplexer, the packet decoder to decode the packets and output the parallel data and the DQS signal;   a set of line drivers coupled to the packet decoder, the set of line drivers to drive data signals corresponding to the parallel data on a set of data lines of the first parallel interface; and   a strobe driver coupled to the packet decoder, the strobe driver to drive the DQS signal on a strobe line of the first parallel interface.   
     
     
         10 . The data buffer device of  claim 2 , wherein the DQS preamble information is programmable to comprise at least one of a plurality of DQS patterns, each DQS pattern corresponding to a different clock cycle (tCKs) duration for a DQS period. 
     
     
         11 . The data buffer device of  claim 2 , wherein the header fields comprises at least one synchronization (sync) packet, a preamble packet, and a start of data packet, wherein the sync packet comprises a first sequence of bits, the preamble packet comprises a second sequence of bits specifying the DQS preamble information, and the start of data packet comprises a third sequence of bits, wherein the first sequence, the second sequence, and the third sequence are different. 
     
     
         12 . A memory system comprising:
 a memory device that operates according to a parallel data and strobe scheme; and   an interface circuit to receive a serial data stream from a host device, the serial data stream comprising header fields that specify data strobe (DQS) preamble information, and convert the serial data stream to the parallel data and a DQS signal associated with the parallel data using the header fields, and output the parallel data and the DQS signal to the memory device.   
     
     
         13 . The memory system of  claim 12 , wherein the interface circuit comprises:
 a serial data terminal coupled to the host device; and   a set of parallel data terminals coupled to data terminals of the memory device; and   a strobe terminal coupled to a strobe terminal of the memory device.   
     
     
         14 . The memory system of  claim 13 , wherein the interface circuit further comprises:
 a deserializer circuit to receive the serial data stream and to convert the serial data stream into packets, wherein the packets comprise at least the parallel data and a preamble packet;   a latch coupled to an output of the deserializer circuit to store the packets;   a packet decoder coupled to the latch, the packet decoder to decode the packets and output the parallel data and the DQS signal;   a set of line drivers coupled to the packet decoder, the set of line drivers to drive data signals corresponding to the parallel data on the set of parallel data terminals; and   a strobe driver coupled to the packet decoder, the strobe driver to drive the DQS signal on the strobe terminal.   
     
     
         15 . The memory system of  claim 14 , wherein the packet decoder comprises a finite state machine (FSM). 
     
     
         16 . The memory system of  claim 14 , wherein the deserializer circuit is a 1: N deserializer, where N is an integer greater than one. 
     
     
         17 . The memory system of  claim 12 , wherein the header fields comprises:
 one or more synchronization packets, each synchronization packet comprising a first binary sequence of bits;   a synchronization and preamble packet comprising a second binary sequence of bits; and   a start of data transfer packet comprising a third binary sequence of bits.   
     
     
         18 . The memory system of  claim 12 , wherein the header fields are one or more clock cycles in duration, wherein the header fields comprises zero or more synchronization packets, a synchronization and preamble packet, and a start of data transfer packet. 
     
     
         19 . A method of operating an interface circuit of a data buffer device, the method comprising:
 receiving, from a host device, a serial data stream over a first serial interface, the serial data stream comprising header fields inserted into the serial data stream, wherein the header fields specify data strobe (DQS) preamble information;   converting, using the header fields, the serial data stream to parallel data and a DQS signal associated with the parallel data; and   outputting, to a memory device, the parallel data and the DQS signal over a first parallel interface.   
     
     
         20 . The method of  claim 19 , further comprising:
 receiving, from the memory device, second parallel data over the first parallel interface;   converting the second parallel data to a second serial data stream; and   outputting, to the host device, the second serial data stream over the first serial interface.   
     
     
         21 . The method of  claim 19 , further comprising:
 receiving, from the memory device, second parallel data over a second parallel interface;   converting the second parallel data to a second serial data stream; and   outputting, to the host device, the second serial data stream over a second serial interface.