Processing-in-memory devices

Abstract

A processing-in-memory device includes a memory cell array including a plurality of memory cells coupled to a plurality of word lines and a plurality of bit lines, a sense amplifier circuit coupled to the plurality of bit lines, and a control circuit configured to perform a row data copy operation that copies data of a first word line to a second word line, among the plurality of word lines. The control circuit is configured to sequentially perform operations according to an active control signal, a row close control signal, and a row open control signal to perform the row data copy operation.

What is claimed is: 
     
         1 . A processing-in-memory (PIM) device comprising:
 a memory cell array including a plurality of memory cells coupled to a plurality of word lines and a plurality of bit lines;   a sense amplifier circuit coupled to the plurality of bit lines; and   a control circuit configured to perform a row data copy operation that copies data of a first word line to a second word line, among the plurality of word lines,   wherein the control circuit is configured to sequentially perform operations according to an active control signal, a row close control signal, and a row open control signal to perform the row data copy operation.   
     
     
         2 . The processing-in-memory (PIM) device of  claim 1 , wherein the control circuit is configured to activate the first word line and to enable the sense amplifier circuit, based on the active control signal, the data of the memory cells of the first word line being sensed and amplified in the sense amplifier circuit. 
     
     
         3 . The processing-in-memory (PIM) device of  claim 2 , wherein, based on the row close control signal, the control circuit is configured to control the first word line to be closed. 
     
     
         4 . The processing-in-memory (PIM) device of  claim 3 , wherein, based on the row open control signal, the control circuit is configured to control the second word line to be opened, the data sensed and amplified in the sense and amplifier circuit being stored in the memory cells of the second word line. 
     
     
         5 . The processing-in-memory (PIM) device of  claim 4 , wherein the control circuit is configured to disable the sense amplifier circuit based on a precharge control signal. 
     
     
         6 . The processing-in-memory (PIM) device of  claim 1 ,
 wherein the sense amplifier circuit includes a plurality of sense amplifiers respectively coupled to the plurality of bit lines,   wherein the control circuit includes:   a row control circuit configured to, in response to the active control signal at a first logic level, transmit a first row control signal for activating the first word line designated by a first row address signal to the memory cell array; and   a sense amplifier control signal configured to, in response to the active control signal at the first logic level, transmit a switching-on signal for turning on the sense amplifiers to the sense amplifier circuit, and   wherein the turned-on sense amplifiers are configured to sense and amplify data of the memory cells of the activated first word line.   
     
     
         7 . The processing-in-memory (PIM) device of  claim 6 , wherein the row control circuit is configured to:
 transmit a second row control signal for controlling the first word line to be closed to the memory cell array in response to the row close control signal at the first logic level, and   transmit a third row control signal for controlling the second word line to be opened to the memory cell array in response to the row open control signal at the first logic level, the data sensed and amplified by the second amplifiers being stored in the memory cells of the second word line.   
     
     
         8 . The processing-in-memory (PIM) device of  claim 7 , wherein the sense amplifier control circuit is configured to transmit a switching-off signal for disabling the sense amplifier circuit to the sense amplifier circuit in response to the precharge control signal at the first logic level. 
     
     
         9 . The processing-in-memory (PIM) device of  claim 1 , further comprising an operating circuit configured to receive data of the memory cell array to perform operations,
 wherein the operating circuit is configured to receive the data sensed and amplified by the second amplifiers between a time point at which the first word line is closed and a time point at which the second word line is opened and configured to perform the operations using the received data.   
     
     
         10 . The processing-in-memory (PIM) device of  claim 9 ,
 wherein the operating circuit is configured to transmit operation result data generated as a result of performing the operations to the sense amplifiers, and   wherein the row control circuit is configured to, in response to the row open control signal at the first logic level to the memory cell array, transmit a third row control signal for controlling a third word line designated by a third row address signal to be opened, the operation result data transmitted to the sense amplifiers being stored in memory cells of the third word line.   
     
     
         11 . A processing-in-memory (PIM) device comprising:
 sub memory cell arrays, each including a plurality of memory cells coupled to a plurality of word lines and a plurality of bit lines, the sub memory cell arrays including a first sub memory cell array including a plurality of first memory cells coupled to a plurality of first word lines and a plurality of first bit lines and a plurality of second sub memory cell array including a plurality of second memory cells coupled to a plurality of second word lines and a plurality of second bit lines;   a first sense amplifier circuit coupled to the plurality of first bit lines of the first sub memory cell array;   a second sense amplifier circuit coupled to the plurality of second bit lines of the second sub memory cell array;   a copy circuit configured to, based on a copy control signal, control an electrical connection of the plurality of first bit lines and the plurality of second bit lines;   a copy control circuit configured to generate the copy control signal based on a first row open control signal, a first row close control signal, a second row open control signal, and a second row close control and configured to transmit the copy control signal to the copy circuit; and   a control circuit configured to control a row data copy operation between the sub memory cell arrays by copying data of the first memory cells of a source word line, which is one of the plurality of first word lines, to the second memory cells of a target word line, which is one of the plurality of second word lines,   wherein the control circuit is configured to sequentially perform operations between the sub memory cell arrays according to a first active control signal, the first row close control signal, the second row open control signal, and the copy control signal to perform the row data copy operation.   
     
     
         12 . The processing-in-memory (PIM) device of  claim 11 , wherein the control circuit is configured to:
 control the first sub memory cell array and the first sense amplifier circuit in response to the first active control signal at a first logic level, the source word line of the first sub memory cell array being activated and the first sense amplifier circuit being enabled,   control the first sub memory cell array in response to the first row close signal at the first logic level, the source word line of the first sub memory cell array being closed;   control the second sub memory cell array, the target word line of the second sub memory cell array being opened, and control the copy circuit, the first bit lines and the second bit lines being electrically connected, in response to the second row open control signal at the first logic level, and   control the second sub memory cell array in response to the second row close control signal at the first logic level, the target word line of the second sub memory cell array being closed.   
     
     
         13 . The processing-in-memory (PIM) device of  claim 11 , wherein the control circuit includes:
 a first control circuit configured to receive the first active control signal, a first precharge control signal, the first row open control signal, and the first row close control signal and configured to generate and transmit a first row control signal and a first switching signal to the first sub memory cell array and the first sense amplifier circuit, respectively; and   a second control circuit configured to receive a second active control signal, a second precharge control signal, the second row open control signal, and the second row close control signal and configured to generate and transmit a second row control signal and a second switching signal to the second sub memory cell array and the second sense amplifier circuit, respectively.   
     
     
         14 . The processing-in-memory (PIM) device of  claim 13 ,
 wherein the first control circuit includes:   a first row control circuit configured to generate the first row control signal based on the first active control signal, the first precharge control signal, the first row open control signal, and the first row close control signal and configured to transmit the first row control signal to the first sub memory cell array; and   a first sense amplifier control circuit configured to generate the first switching signal based on the first active control signal and the first precharge control signal and configured to transmit the first switching signal to the first sense amplifier circuit, and   wherein the second control circuit includes:   a second row control circuit configured to generate the second row control signal based on the second active control signal, the second precharge control signal, the second row open control signal, and the second row close control signal and configured to transmit the second row control signal to the second sub memory cell array; and   a second sense amplifier control circuit configured to generate the second switching signal based on the second active control signal and the second precharge control signal and configured to transmit the second switching signal to the second sense amplifier circuit.   
     
     
         15 . The processing-in-memory (PIM) device of  claim 14 ,
 wherein the first row control circuit is configured to:   transmit the first row control signal for activating the source word line to the first sub memory cell array, in response to the first active control signal at a first logic level,   transmit the first row control signal for closing the source word line to the first sub memory cell array, in response to the first precharge control signal at the first logic level,   transmit the first row control signal for opening the source word line to the first sub memory cell array, in response to the first row open control signal at the first logic level, and   transmit the first row control signal for closing the source word line to the first sub memory cell array, in response to the first row close control signal at the first logic level, and   wherein the second row control circuit is configured to:   transmit the second row control signal for activating the target word line to the second sub memory cell array, in response to the second active control signal at the first logic level,   transmit the second row control signal for closing the target word line to the second sub memory cell array, in response to the second precharge control signal at the first logic level,   transmit the second row control signal for opening the target word line to the second sub memory cell array, in response to the second row open control signal at the first logic level, and   transmit the second row control signal for closing the target word line to the second sub memory cell array, in response to the second row close control signal at the first logic level.   
     
     
         16 . The processing-in-memory (PIM) device of  claim 15 ,
 wherein the first sense amplifier control circuit is configured to:   transmit the first switching signal for enabling the first sense amplifier circuit to the first sense amplifier circuit, in response to the first active control signal at the first logic level, and   transmit the first switching signal for disabling the first sense amplifier circuit to the first sense amplifier circuit, in response to the first precharge control signal at the first logic level, and   wherein the second sense amplifier control circuit is configured to:   transmit the second switching signal for enabling the second sense amplifier circuit to the second sense amplifier circuit, in response to the second active control signal at the first logic level, and   transmit the second switching signal for disabling the second sense amplifier circuit to the second sense amplifier circuit, in response to the second precharge control signal at the first logic level.   
     
     
         17 . The processing-in-memory (PIM) device of  claim 16 ,
 wherein the copy circuit includes transistors, and   wherein drains of the transistors are coupled to the first bit lines of the first sub memory cell array, sources of the transistors are coupled to the second bit lines of the second sub memory cell array, and gates of the transistors receive the copy control signal in common.   
     
     
         18 . The processing-in-memory (PIM) device of  claim 17 , wherein the copy control circuit is configured to:
 transmit the copy control signal at the first logic level for turning on the transistors to the copy circuit in synchronization with a time point at which the second row open control signal at the first logic level is transmitted, when the first row close control signal at the first logic level and the second row open control signal at the first logic level are transmitted successively, and   transmit the copy control signal at a second logic level for turning off the transistors to the copy circuit in synchronization with a time point at which the second row close control signal at the first logic level is transmitted, when the second row open control signal at the first logic level and the second row close control signal at the first logic level are transmitted successively.   
     
     
         19 . The processing-in-memory (PIM) device of  claim 17 , wherein the copy control circuit is configured to:
 transmit the copy control signal at the first logic level for turning on the transistors to the copy circuit in synchronization with a time point at which the first row open control signal at the first logic level is transmitted, when the second row close control signal at the first logic level and the first row open control signal at the first logic level are transmitted successively, and   transmit the copy control signal at a second logic level for turning off the transistors to the copy circuit in synchronization with a time point at which the first row close control signal at the first logic level is transmitted, when the first row open control signal at the first logic level and the first row close control signal at the first logic level are transmitted successively.   
     
     
         20 . The processing-in-memory (PIM) device of  claim 11 , further comprising:
 a first operating circuit configured to receive data of the first sub memory cell array to perform a first operation; and   a second operating circuit configured to receive data of the second sub memory cell array to perform a second operation.