In-memory computation device with at least an improved digital detector for a more accurate current measurement

Abstract

An in-memory computation device receives an input signal and provides an output signal. The device includes a memory array with memory cells coupled to word lines that receive word line activation signals indicative of the input signal and coupled to bit lines that generate bit line currents; and a digital detector for sampling the bit line current and, in response, providing the output signal. A digital detector includes: a control stage that compares the bit line current with at least one reference current and generates corresponding control signals; a selection stage that generates a total selection current based on the first bit line current and on the control signals; an integration stage that samples the total selection current; and a charge counter stage that generates the output signal on the basis of a sampled first total selection current and the control signals.

1 . An in-memory computation (IMC) device configured to receive an input signal indicative of a plurality of input values and to provide at least an output signal indicative of a plurality of output values, the IMC device comprising:
 a word line activation circuit configured to receive the input signal and to provide a plurality of word line activation signals, each word line activation signal being a function of a respective input value of the input values;   a biasing circuit configured to provide a biasing voltage;   a memory array comprising a plurality of first memory cells coupled to a first bit line and each coupled to a respective word line, the first bit line being configured to receive the biasing voltage, the first memory cells being configured to each store a respective computational weight and to each receive from the respective word line a respective word line activation signal of the plurality of word line activation signals, the first memory cells being configured to be each traversed by a respective cell current which is a function of the biasing voltage, of the respective word line activation signal and of the respective computational weight, the first bit line being configured to be traversed by a first bit line current which is a sum of the cell currents; and   a first digital detector coupled to the first bit line and configured to sample the first bit line current and, in response to the first bit line current, provide the output signal;   wherein the first digital detector comprises:
 a control stage electrically coupled to the first bit line and configured to receive the first bit line current, generate at least a first main control mirrored current in response to the first bit line current, compare the first main control mirrored current with at least a first reference current and generate one or more control signals indicative of said comparison; 
 a selection stage electrically coupled to the control stage and the first bit line and configured to receive the first bit line current and the one or more control signals and generate a total selection current in response to the first bit line current and as a function of the one or more control signals; 
 an integration stage electrically coupled to the selection stage and configured to receive and sample the total selection current; and 
 a charge counter stage electrically coupled to the integration stage and to the control stage and configured to receive the total selection current sampled and the one or more control signals and generate, as a function of the one or more control signals, the output signal in response to the sampled first total selection current. 
   
     
     
         2 . The IMC device according to  claim 1 , wherein the total selection current is lower than, or equal to, the first bit line current. 
     
     
         3 . The IMC device according to  claim 1 , wherein the total selection current is configured to decrease with respect to the first bit line current correspondingly to how much the first bit line current increases. 
     
     
         4 . The IMC device according to  claim 1 , wherein the control stage is further configured to generate at least a second main control mirrored current in response to the first bit line current, compare the second main control mirrored current with a second reference current and generate said control signals indicative of the comparison of the first main control mirrored current with the first reference current and of the second main control mirrored current with the second reference current. 
     
     
         5 . The IMC device according to  claim 4 , wherein the control stage and the selection stage comprise a main current mirror electrically coupled to the first bit line and configured to receive the first bit line current and to mirror it in at least a first and a second control input branch of the control stage and in at least a first, a second and a third selection input branch of the selection stage. 
     
     
         6 . The IMC device according to  claim 5 :
 wherein the main current mirror has a same main control mirror ratio for both the first control input branch and the second control input branch of the control stage;   wherein the first and the second main control mirrored currents are generated in response to the first bit line current and on the basis of the main control mirror ratio, the first main control mirrored current is configured to flow in the first control input branch up to a first control input node of the control stage and the second main control mirrored current is configured to flow in the second control input branch up to a second control input node of the control stage;   wherein the control stage further comprises a secondary current mirror configured to receive a biasing current and to mirror it into a first output branch and a second output branch of the control stage;   wherein the secondary current mirror has a first secondary control mirror ratio for the first output branch and a second secondary control mirror ratio for the second output branch in such a way that a first secondary control mirrored current flows through the first output branch and a second secondary control mirrored current through the second output branch, the first secondary control mirrored current being greater than the second secondary control mirrored current, the first secondary control mirrored current being said first reference current and the second secondary control mirrored current being said second reference current; and   wherein the first control input node is shared between the first output branch and the first control input branch and the second control input node is shared between the second output branch and the second control input branch.   
     
     
         7 . The IMC device according to  claim 6 , wherein the control stage further comprises:
 a first control inverter and a second control inverter respectively coupled to the first control input node and the second control input node;   a first control flip-flop and a second control flip-flop, each control flip-flop having a respective input coupled, respectively, to the first control input node and the second control input node through, respectively, the first control inverter and the second control inverter; and   a set of control logic gates which is coupled to outputs of the first control flip-flop and the second control flip-flop, to the charge counter stage and to the selection stage and is configured to generate the control signals on the basis of the outputs of the first control flip-flop and the second control flip-flop.   
     
     
         8 . The IMC device according to  claim 7 :
 wherein the control signals comprise a first control signal, a second control signal, a third control signal and a first negated control signal;   wherein the first control signal assumes a first logic value when the output of the first control flip-flop and the output of the second control flip-flop assume first logic values, and assumes a second logic value when the output of the first control flip-flop and the output of the second control flip-flop assume second logic values or when the output of the first control flip-flop assumes the second logic value and the output of the second control flip-flop assumes the first logic value,   wherein the second control signal assumes the first logic value when the output of the first control flip-flop assumes the second logic value and the output of the second control flip-flop assumes the first logic value, and assumes the second logic value when the output of the first control flip-flop and the output of the second control flip-flop assume the first or the second logic values;   wherein the third control signal assumes the first logic value when the output of the first control flip-flop and the output of the second control flip-flop assume the second logic values, and assumes the second logic value when the output of the first control flip-flop and the output of the second control flip-flop assume the first logic values or when the output of the first control flip-flop assumes the second logic value and the output of the second control flip-flop assumes the first logic value; and   wherein the first negated control signal assumes the first logic value when the first control signal assumes the second logic value and assumes the second logic value when the first control signal assumes the first logic value.   
     
     
         9 . The IMC device according to  claim 5 :
 wherein the main current mirror has a respective selection mirror ratio for each of the first selection input branch, the second selection input branch and the third selection input branch of the selection stage in such a way that in the first selection input branch, in the second selection input branch and in the third selection input branch a first selection mirrored current, a second selection mirrored current and a third selection mirrored current respectively flow;   wherein the first selection input branch, the second selection input branch and the third selection input branch share a selection common node through which the total selection current is configured to flow; and   wherein the selection stage comprises one or more selection switches which extend along at least some of the first selection input branch, the second selection input branch and the third selection input branch and are configured to receive the control signals and selectively switch as a function of the control signals in such a way as to generate at the selection common node corresponding mutual combinations, different from and alternative to each other, of the selection mirrored current, of the second selection mirrored current, and of the third selection mirrored current, the total selection current in the selection common node being defined at each time by the respective combination of the selection mirrored current, of the second selection mirrored current and of the third selection mirrored current.   
     
     
         10 . The IMC device according to  claim 1 , wherein the charge counter stage comprises:
 one or more count selectors which are coupled to the integration stage to receive a negated clock signal indicative of the sampling of the total selection current, are coupled to the control stage to receive the control signals and are controllable as a function of the control signals; and   a plurality of count flip-flops coupled to the one or more count selectors and configured to receive respective flip-flop input signals generated by the count selectors as a function of the control signals and generate the output signal on the basis of said flip-flop input signals.   
     
     
         11 . The IMC device according to  claim 10 :
 wherein the control stage is further configured to generate at least a second main control mirrored current in response to the first bit line current, compare the second main control mirrored current with a second reference current and generate said control signals indicative of the comparison of the first main control mirrored current with the first reference current and of the second main control mirrored current with the second reference current;   wherein the count selectors comprise a first count selector, a second count selector and a third count selector;   wherein each count selector has a respective first input coupled to the integration stage to receive the negated clock signal, a respective second input, a respective control input coupled to the control stage to receive a respective control signal of the control signals, and a respective output, the one or more count selectors each being configured to selectively couple the output with one of the first input and the second input as a function of the control signal at the control input;   wherein the second input of the first count selector is configured to receive a predefined logic signal;   wherein the plurality of count flip-flops comprises a first count flip-flop, a second count flip-flop, a third count flip-flop, and an F-th count flip-flop, cascading with each other;   wherein each count flip-flop has a clock input, a data input, a first output and a second output;   wherein the second input of the second count selector and the third count selector is coupled to the second output of the first count selector and the second count selector, respectively;   wherein the clock input of the first count flip-flop, the second count flip-flop and the third count flip-flop is respectively connected to the output of the first count selector, the second count selector and the third count selector and the clock input of the F-th count flip-flop is connected to the second output of the immediately preceding count flip-flop, the clock inputs of the count flip-flops being configured to receive said flip-flop input signals;   wherein the data input of the first count flip-flop, the second count flip-flop, the third count flip-flop and the F-th count flip-flop is respectively connected to the second output of the first count flip-flop, the second count flip-flop, the third count flip-flop and the F-th count flip-flop; and   wherein the first outputs of the count flip-flops are configured to generate the output signal.   
     
     
         12 . The IMC device according to  claim 1 :
 wherein the control stage is further configured to generate at least a second main control mirrored current in response to the first bit line current, compare the second main control mirrored current with a second reference current and generate said control signals indicative of the comparison of the first main control mirrored current with the first reference current and of the second main control mirrored current with the second reference current; and   wherein the control stage is further configured to generate at least a third main control mirrored current in response to the first bit line current, compare the third main control mirrored current with at least a third reference current, and generate the control signals also indicative of the comparison with the third reference current.   
     
     
         13 . The IMC device according to  claim 1 , wherein the digital detector is configured to perform a number of successive sampling iterations and, in each sampling iteration:
 the integration stage is configured to generate an integration signal indicative of a time integral of the first total selection current, compare the integration signal with a sampling threshold and reset the integration signal in response to the integration signal reaching the sampling threshold;   the integration stage comprises a first inverter having an output providing the integration signal, and an integration capacitive element coupled to the output of the first inverter, the first inverter being configured to receive the total selection current indicative of the bit line current; and   the charge counter stage is configured to update the output signal in response to the integration signal reaching the sampling threshold.   
     
     
         14 . The IMC device according to  claim 1 :
 wherein the biasing circuit is configured to provide the biasing voltage in response to a reference current;   wherein the biasing circuit comprises a reference network having a variable reference impedance and configured to be traversed by the reference current, the biasing voltage being a function of the reference current and the variable reference impedance; and   wherein the reference network comprises a reference memory array configured to have a reference transconductance value, the variable reference impedance being a function of the reference transconductance value, the reference memory array representing a statistically significant sample of the memory array.   
     
     
         15 . The IMC device according to  claim 1 :
 wherein the word line activation circuit comprises a timer configured to provide a timer signal, and a plurality of input-to-time converters electrically coupled to the timer and configured to receive the timer signal, each compare the timer signal with the respective input value of the input values and, in response, each provide the respective word line activation signal;   wherein the timer comprises a respective integration stage; and   wherein the integration stage of the digital detector has the same circuit diagram as the integration stage of the timer.   
     
     
         16 . The IMC device according to  claim 1 :
 wherein the memory array further comprises a plurality of second memory cells coupled to a second bit line and each coupled to a respective word line of the word lines, the second bit line being configured to receive the biasing voltage, the second memory cells being configured to each store a respective computational weight and to each receive a respective word line activation signal of the plurality of word line activation signals from the respective word line, the second memory cells being configured to be each traversed by a respective cell current which is a function of the biasing voltage, of the respective word line activation signal and of the respective computational weight, the second bit line being configured to be traversed by a second bit line current which is a sum of the cell currents of the second memory cells;   wherein the IMC device further comprises a second digital detector coupled to the second bit line and configured to sample the second bit line current and, in response to the second bit line current, provide the output signal; and   wherein the second digital detector comprises:
 a respective control stage electrically coupled to the second bit line and configured to receive the second bit line current, generate at least a respective first main control mirrored current in response to the second bit line current, compare the respective first main control mirrored current with at least one respective first reference current and generate one or more respective control signals indicative of said comparison; 
 a respective selection stage electrically coupled to the control stage of the second digital detector and to the second bit line and configured to receive the second bit line current and the one or more respective control signals and generate a respective total selection current in response to the second bit line current and as a function of one or more respective control signals; 
 a respective integration stage electrically coupled to the selection stage of the second digital detector and configured to receive and sample the respective total selection current; and 
 a respective charge counter stage electrically coupled to the integration stage and to the control stage of the second digital detector and configured to receive the respective total selection current sampled and the one or more respective control signals and generate, as a function of the one or more respective control signals, the output signal in response to the sampling of the second total selection current. 
   
     
     
         17 . A method for controlling the (IMC) device of  claim 1 , comprising:
 providing, by the word line activation circuit, the plurality of word line activation signals to the first memory cells;   generating, by the biasing circuit, the biasing voltage and applying the biasing voltage to the first bit line;   generating, by the control stage, the at least a first main control mirrored current in response to the first bit line current;   comparing, by the control stage, the at least a first main control mirrored current with the at least a first reference current;   generating, by the control stage, the one or more control signals indicative of said comparison;   generating, by the selection stage, the total selection current in response to the first bit line current and as a function of the one or more control signals;   sampling, by the integration stage, the total selection current; and   generating, by the charge counter stage and as a function of the one or more control signals, the output signal in response to sampling the first total selection current.